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  • SN74AUP1G79 Low-Power Single Positive-Edge-Triggered D-Type Flip-Flop

    • SCES592I July   2004  – September 2017 SN74AUP1G79

      PRODUCTION DATA.  

  • CONTENTS
  • SEARCH
  • SN74AUP1G79 Low-Power Single Positive-Edge-Triggered D-Type Flip-Flop
  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: TA = 25°C
    6. 6.6  Electrical Characteristics: TA = -40°C to 85°C
    7. 6.7  Timing Requirements
    8. 6.8  Switching Characteristics: CL = 5 pF
    9. 6.9  Switching Characteristics: CL = 10 pF
    10. 6.10 Switching Characteristics: CL = 15 pF
    11. 6.11 Switching Characteristics: CL = 30 pF
    12. 6.12 Operating Characteristics
    13. 6.13 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Propagation Delays, Setup and Hold Times, and Pulse Width
    2. 7.2 Enable and Disable Times
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Balanced CMOS Push-Pull Outputs
      2. 8.3.2 Standard CMOS Inputs
      3. 8.3.3 Clamp Diodes
      4. 8.3.4 Partial Power Down (Ioff)
      5. 8.3.5 Over-voltage Tolerant Inputs
    4. 8.4 Device Functional Modes
  9. 9 Applications, Implementation, and Layout
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information
  14. IMPORTANT NOTICE

封装选项

机械数据 (封装 | 引脚)
  • DRY|6
    • MPDS221F
  • DRL|5
    • MPDS158G
  • DSF|6
    • MPDS301G
  • DPW|5
    • MPSS088
  • DCK|5
    • MPDS025K
  • DBV|5
    • MPDS018T
散热焊盘机械数据 (封装 | 引脚)
  • DRY|6
    • QFND138E
  • DPW|5
    • QFND567C
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DATA SHEET

SN74AUP1G79 Low-Power Single Positive-Edge-Triggered D-Type Flip-Flop

1 Features

  • Available in the Texas Instruments NanoStar™ Package
  • Low Static-Power Consumption:
    ICC = 0.9 µA Maximum
  • Low Dynamic-Power Consumption:
    Cpd = 3 pF Typical at 3.3 V
  • Low Input Capacitance:
    Ci = 1.5 pF Typical
  • Low Noise: Overshoot and Undershoot
    < 10% of VCC
  • Ioff Supports Partial Power-Down-Mode Operation
  • Input Hysteresis Allows Slow Input Transition and Better Switching Noise Immunity at the Input
    (Vhys = 250 mV Typical at 3.3 V)
  • Wide Operating VCC Range of 0.8 V to 3.6 V
  • Optimized for 3.3-V Operation
  • 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
  • tpd = 4 ns Maximum at 3.3 V
  • Suitable for Point-to-Point Applications
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Performance Tested Per JESD 22
    • 2000-V Human-Body Model
      (A114-B, Class II)
    • 1000-V Charged-Device Model (C101)

2 Applications

  • Barcode Scanner
  • Cable Solutions
  • E-Book
  • Embedded PC
  • Field Transmitter: Temperature or Pressure Sensor
  • Fingerprint Biometrics
  • HVAC: Heating, Ventilating, and Air Conditioning
  • Network-Attached Storage (NAS)
  • Server Motherboard and PSU
  • Software Defined Radio (SDR)
  • TV: High-Definition (HDTV), LCD, and Digital
  • Video Communications System
  • Wireless Data Access Card, Headset, Keyboard, Mouse, and LAN Card

3 Description

The AUP family is TI's premier solution to the industry's low-power needs in battery-powered portable applications. This family assures a very-low static and dynamic power consumption across the entire VCC range of 0.8 V to 3.6 V, thus resulting in an increased battery life. The AUP devices also maintain excellent signal integrity.

The SN74AUP1G79 is a single positive-edge-triggered D-type flip-flop. When data at the data (D) input meets the setup-time requirement, the data is transferred to the Q output on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.

NanoStar™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

The SN74AUP1G79 device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs when the device is powered down. This inhibits current backflow into the device which prevents damage to the device.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
SN74AUP1G79DBV SOT-23 (5) 2.90 mm × 1.60 mm
SN74AUP1G79DCK SC70 (5) 2.00 mm × 1.25 mm
SN74AUP1G79DRL SOT-5X3 (5) 1.60 mm × 1.20 mm
SN74AUP1G79DRY SON (6) 1.45 mm × 1.00 mm
SN74AUP1G79DSF SON (6) 1.00 mm × 1.00 mm
SN74AUP1G79DPW X2SON (5) 0.80 mm x 0.80 mm
SN74AUP1G79YFP DSBGA (6) 1.16 mm × 0.76 mm
SN74AUP1G79YZP DSBGA (5) 1.39 mm × 0.89 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Power Consumption and Performance

SN74AUP1G79 ex_sig_int_ces592.gif

4 Revision History

Changes from H Revision (April 2015) to I Revision

  • Added DPW (X2SON) packageGo
  • Added Maximum junction temperature, TJ in Absolute Maximum RatingsGo
  • Changed values in the Thermal Information table to align with JEDEC standards. Go
  • Added Balanced High-Drive CMOS Push-Pull Outputs, Standard CMOS Inputs, Clamp Diodes, Partial Power Down (Ioff), Over-voltage Tolerant InputsGo
  • Added Receiving Notification of Documentation Updates and Community ResourcesGo

Changes from G Revision (May 2010) to H Revision

  • Updated document to the new TI data sheet formatGo
  • Removed Ordering Information table Go
  • Added Device Information table Go
  • Added Typical Characteristics sectionGo

5 Pin Configuration and Functions

DBV Package
5-Pin SOT-23
Top View
SN74AUP1G79 po1_ces592.gif
DCK Package
5-Pin SC70
Top View
SN74AUP1G79 po3_ces592.gif
DRL Package
5-Pin SOT-5X3
Top View
SN74AUP1G79 po5_ces592.gif
DPW Package
5-Pin X2SON
Top View
SN74AUP1G79 DPW_Pinout.gif
DRY Package
6-Pin SON
Top View
SN74AUP1G79 po2_ces592.gif
DSF Package
6-Pin SON
Top View
SN74AUP1G79 po4_ces592.gif
YFP Package
6-Pin DSBGA
Bottom View
SN74AUP1G79 SN74AUP1G79-yfp-pinout.gif
YZP Package
5-Pin DSBGA
Bottom View
SN74AUP1G79 SN74AUP1G79-yzp-pinout.gif

Pin Functions

PIN I/O DESCRIPTION
NAME DBV, DCK,
DRL, DPW		 DRY,
DSF		 YZP YFP
CLK 2 2 B1 B1 I Positive-Edge-Triggered Clock input
D 1 1 A1 A1 I Data Input
GND 3 3 C1 C1 — Ground pin
NC — 5 — B2 — No Connect
Q 4 4 C2 C2 O Q output
VCC 5 6 A2 A2 — Positive supply

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VCC Supply voltage –0.5 4.6 V
VI Input voltage(2) –0.5 4.6 V
VO Voltage range applied to any output in the high-impedance or power-off state(2) –0.5 4.6 V
VO Output voltage range in the high or low state(2) –0.5 VCC + 0.5 V
IIK Input clamp current VI < 0 –50 mA
IOK Output clamp current VO < 0 –50 mA
IO Continuous output current ±20 mA
Continuous current through VCC or GND ±50 mA
TJ Maximum junction temperature 150 °C
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) 2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) 1000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

MIN MAX UNIT
VCC Supply voltage 0.8 3.6 V
VIH High-level input voltage VCC = 0.8 V VCC V
VCC = 1.1 V to 1.95 V 0.65 × VCC
VCC = 2.3 V to 2.7 V 1.6
VCC = 3 V to 3.6 V 2
VIL Low-level input voltage VCC = 0.8 V 0 V
VCC = 1.1 V to 1.95 V 0.35 × VCC
VCC = 2.3 V to 2.7 V 0.7
VCC = 3 V to 3.6 V 0.9
VI Input voltage(1) 0 3.6 V
VO Output voltage 0 VCC V
IOH High-level output current VCC = 0.8 V –20 µA
VCC = 1.1 V –1.1 mA
VCC = 1.4 V –1.7
VCC = 1.65 V –1.9
VCC = 2.3 V –3.1
VCC = 3 V –4
IOL Low-level output current VCC = 0.8 V 20 µA
VCC = 1.1 V 1.1 mA
VCC = 1.4 V 1.7
VCC = 1.65 V 1.9
VCC = 2.3 V 3.1
VCC = 3 V 4
Δt/Δv Input transition rise or fall rate VCC = 0.8 V to 3.6 V 200 ns/V
TA Operating free-air temperature –40 85 °C
(1) All unused inputs of the device must be held at VCC or GND to assure proper device operation. See the TI application report, Implications of Slow or Floating CMOS Inputs.

6.4 Thermal Information

THERMAL METRIC(1) SN74AUP1G79 UNIT
DBV
(SOT-23)		 DCK
(SC70)		 DRL
(SOT-5X3)		 DRY
(SON)		 DSF
(SON)		 DPW
(X2SON)		 YFP
(DSBGA)		 YZP
(DSBGA)
5 PINS 5 PINS 5 PINS 6 PINS 6 PINS 5 PINS 6 PINS 5 PINS
RθJA Junction-to-ambient thermal resistance 267.2 284.1 294.1 341.1 377.1 489.2 125.4 146.2 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 191.9 208.5 132.5 233.1 187.7 226.3 1.9 1.4 °C/W
RθJB Junction-to-board thermal resistance 101.1 103.1 143.4 206.7 236.6 352.9 37.2 39.3 °C/W
ψJT Junction-to-top characterization parameter 83.0 76.6 14.5 63.4 29.0 38.2 0.5 0.7 °C/W
ψJB Junction-to-board characterization parameter 100.8 102.3 143.9 206.7 236.3 352.1 37.5 39.8 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A N/A N/A N/A 150.8 N/A N/A °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Electrical Characteristics: TA = 25°C

over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
VOH IOH = –20 µA 0.8 V to 3.6 V VCC – 0.1 V
IOH = –1.1 mA 1.1 V 0.75 × VCC
IOH = –1.7 mA 1.4 V 1.11
IOH = –1.9 mA 1.65 V 1.32
IOH = –2.3 mA 2.3 V 2.05
IOH = –3.1 mA 1.9
IOH = –2.7 mA 3 V 2.72
IOH = –4 mA 2.6
VOL IOL = 20 µA 0.8 V to 3.6 V 0.1 V
IOL = 1.1 mA 1.1 V 0.3 ×  VCC
IOL = 1.7 mA 1.4 V 0.31
IOL = 1.9 mA 1.65 V 0.31
IOL = 2.3 mA 2.3 V 0.31
IOL = 3.1 mA 0.44
IOL = 2.7 mA 3 V 0.31
IOL = 4 mA 0.44
II D or CLK
input		 VI = GND to 3.6 V 0 V to 3.6 V 0.1 µA
Ioff VI or VO = 0 V to 3.6 V 0 V 0.2 µA
ΔIoff VI or VO = 0 V to 3.6 V 0 V to 0.2 V 0.2 µA
ICC VI = GND or VCC to 3.6 V, IO = 0 0.8 V to 3.6 V 0.5 µA
ΔICC VI = VCC – 0.6 V,(1) IO = 0 3.3 V 40 µA
Ci VI = VCC or GND 0 V 1.5 pF
3.6 V 1.5
Co VO = GND 0 V 3 pF
(1) One-input switching

6.6 Electrical Characteristics: TA = –40°C to 85°C

over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN MAX UNIT
VOH IOH = –20 µA 0.8 V to 3.6 V VCC – 0.1 V
IOH = –1.1 mA 1.1 V 0.7 × VCC
IOH = –1.7 mA 1.4 V 1.03
IOH = –1.9 mA 1.65 V 1.3
IOH = –2.3 mA 2.3 V 1.97
IOH = –3.1 mA 1.85
IOH = –2.7 mA 3 V 2.67
IOH = –4 mA 2.55
VOL IOL = 20 µA 0.8 V to 3.6 V 0.1 V
IOL = 1.1 mA 1.1 V 0.3 ×  VCC
IOL = 1.7 mA 1.4 V 0.37
IOL = 1.9 mA 1.65 V 0.35
IOL = 2.3 mA 2.3 V 0.33
IOL = 3.1 mA 0.45
IOL = 2.7 mA 3 V 0.33
IOL = 4 mA 0.45
II D or CLK
input		 VI = GND to 3.6 V 0 V to 3.6 V 0.5 µA
Ioff VI or VO = 0 V to 3.6 V 0 V 0.6 µA
ΔIoff VI or VO = 0 V to 3.6 V 0 V to 0.2 V 0.6 µA
ICC VI = GND or VCC to 3.6 V, IO = 0 0.8 V to 3.6 V 0.9 µA
ΔICC VI = VCC – 0.6 V,(1) IO = 0 3.3 V 50 µA
(1) One-input switching

6.7 Timing Requirements

over recommended operating free-air temperature range, TA = –40°C to +85°C (unless otherwise noted) (see Figure 3)
VCC MIN TYP(1) MAX UNIT
fclock Clock frequency 0.8 V 20 MHz
1.2 V ± 0.1 V 80
1.5 V ± 0.1 V 100
1.8 V ± 0.15 V 140
2.5 V ± 0.2 V 210
3.3 V ± 0.3 V 260
tw Pulse duration, CLK high or low 0.8 V 4.8 ns
1.2 V ± 0.1 V 2.2
1.5 V ± 0.1 V 1.5
1.8 V ± 0.15 V 1.6
2.5 V ± 0.2 V 1.7
3.3 V ± 0.3 V 1.9
tsu Setup time before CLK↑ Data high 0.8 V 4.2 2.9 ns
1.2 V ± 0.1 V 1.4
1.5 V ± 0.1 V 1
1.8 V ± 0.15 V 0.9
2.5 V ± 0.2 V 0.7
3.3 V ± 0.3 V 0.6
Data low 0.8 V 5.3 3.5
1.2 V ± 0.1 V 1.8
1.5 V ± 0.1 V 1.2
1.8 V ± 0.15 V 1.1
2.5 V ± 0.2 V 1
3.3 V ± 0.3 V 1
th Hold time, data after CLK↑ 0.8 V 0 0 ns
1.2 V ± 0.1 V 0
1.5 V ± 0.1 V 0
1.8 V ± 0.15 V 0
2.5 V ± 0.2 V 0
3.3 V ± 0.3 V 0
(1) TA = 25°C

6.8 Switching Characteristics: CL = 5 pF

over recommended operating free-air temperature range, CL = 5 pF (unless otherwise noted) (see Figure 3 and Figure 4)
PARAMETER FROM
(INPUT)		 TO
(OUTPUT)		 TEST CONDITIONS MIN TYP MAX UNIT
fmax VCC = 0.8 V TA = 25°C 93 MHz
TA = –40°C to +85°C 90
VCC = 1.2 V ± 0.1 V TA = 25°C 199
TA = –40°C to +85°C 220
VCC = 1.5 V ± 0.1 V TA = 25°C 250
TA = –40°C to +85°C 230
VCC = 1.8 V ± 0.15 V TA = 25°C 271
TA = –40°C to +85°C 240
VCC = 2.5 V ± 0.2 V TA = 25°C 280
TA = –40°C to +85°C 250
VCC = 3.3 V ± 0.3 V TA = 25°C 280
TA = –40°C to +85°C 260
tpd CLK Q VCC = 0.8 V TA = 25°C 15.9 ns
VCC = 1.2 V ± 0.1 V TA = 25°C 3.7 6.9 11
TA = –40°C to +85°C 2.6 13.1
VCC = 1.5 V ± 0.1 V TA = 25°C 3 4.8 7.6
TA = –40°C to +85°C 2 8.8
VCC = 1.8 V ± 0.15 V TA = 25°C 2.4 3.8 6.1
TA = –40°C to +85°C 1.5 7.1
VCC = 2.5 V ± 0.2 V TA = 25°C 1.8 2.7 4.4
TA = –40°C to +85°C 1.1 5
VCC = 3.3 V ± 0.3 V TA = 25°C 1.5 2.1 3.6
TA = –40°C to +85°C 0.9 4

6.9 Switching Characteristics: CL = 10 pF

over recommended operating free-air temperature range, CL = 10 pF (unless otherwise noted) (see Figure 3 and Figure 4)
PARAMETER FROM
(INPUT)		 TO
(OUTPUT)		 TEST CONDITIONS MIN TYP MAX UNIT
fmax VCC = 0.8 V TA = 25°C 62 MHz
TA = –40°C to +85°C 50
VCC = 1.2 V ± 0.1 V TA = 25°C 147
TA = –40°C to +85°C 160
VCC = 1.5 V ± 0.1 V TA = 25°C 189
TA = –40°C to +85°C 200
VCC = 1.8 V ± 0.15 V TA = 25°C 180
TA = –40°C to +85°C 240
VCC = 2.5 V ± 0.2 V TA = 25°C 260
TA = –40°C to +85°C 250
VCC = 3.3 V ± 0.3 V TA = 25°C 280
TA = –40°C to +85°C 260
tpd CLK Q VCC = 0.8 V TA = 25°C 18 ns
VCC = 1.2 V ± 0.1 V TA = 25°C 4.3 7.8 12.3
TA = –40°C to +85°C 3.2 14.4
VCC = 1.5 V ± 0.1 V TA = 25°C 3.5 5.5 8.4
TA = –40°C to +85°C 2.5 9.8
VCC = 1.8 V ± 0.15 V TA = 25°C 2.8 4.4 6.8
TA = –40°C to +85°C 1.9 8
VCC = 2.5 V ± 0.2 V TA = 25°C 2.2 3.2 5
TA = –40°C to +85°C 1.5 5.7
VCC = 3.3 V ± 0.3 V TA = 25°C 1.8 2.6 4.1
TA = –40°C to +85°C 1.3 4.5

6.10 Switching Characteristics: CL = 15 pF

over recommended operating free-air temperature range, CL = 15 pF (unless otherwise noted) (see Figure 3 and Figure 4)
PARAMETER FROM
(INPUT)		 TO
(OUTPUT)		 TEST CONDITIONS MIN TYP MAX UNIT
fmax VCC = 0.8 V TA = 25°C 48 MHz
TA = –40°C to +85°C 30
VCC = 1.2 V ± 0.1 V TA = 25°C 112
TA = –40°C to +85°C 120
VCC = 1.5 V ± 0.1 V TA = 25°C 151
TA = –40°C to +85°C 160
VCC = 1.8 V ± 0.15 V TA = 25°C 194
TA = –40°C to +85°C 220
VCC = 2.5 V ± 0.2 V TA = 25°C 248
TA = –40°C to +85°C 250
VCC = 3.3 V ± 0.3 V TA = 25°C 280
TA = –40°C to +85°C 260
tpd CLK Q VCC = 0.8 V TA = 25°C 20.3 ns
VCC = 1.2 V ± 0.1 V TA = 25°C 5 8.7 13.6
TA = –40°C to +85°C 3.9 15.6
VCC = 1.5 V ± 0.1 V TA = 25°C 4.1 6.3 9.3
TA = –40°C to +85°C 3.1 10.7
VCC = 1.8 V ± 0.15 V TA = 25°C 3.3 4 7.6
TA = –40°C to +85°C 2.4 8.7
VCC = 2.5 V ± 0.2 V TA = 25°C 2.6 3.6 5.5
TA = –40°C to +85°C 1.9 6.3
VCC = 3.3 V ± 0.3 V TA = 25°C 2.2 3 4.5
TA = –40°C to +85°C 1.6 5

6.11 Switching Characteristics: CL = 30 pF

over recommended operating free-air temperature range, CL = 30 pF (unless otherwise noted) (see Figure 3 and Figure 4)
PARAMETER FROM
(INPUT)		 TO
(OUTPUT)		 TEST CONDITIONS MIN TYP MAX UNIT
fmax VCC = 0.8 V TA = 25°C 24 MHz
TA = –40°C to +85°C 20
VCC = 1.2 V ± 0.1 V TA = 25°C 72
TA = –40°C to +85°C 80
VCC = 1.5 V ± 0.1 V TA = 25°C 100
TA = –40°C to +85°C 100
VCC = 1.8 V ± 0.15 V TA = 25°C 127
TA = –40°C to +85°C 140
VCC = 2.5 V ± 0.2 V TA = 25°C 185
TA = –40°C to +85°C 210
VCC = 3.3 V ± 0.3 V TA = 25°C 266
TA = –40°C to +85°C 260
tpd CLK Q VCC = 0.8 V TA = 25°C 27.2 ns
VCC = 1.2 V ± 0.1 V TA = 25°C 7 11.5 17.3
TA = –40°C to +85°C 5.9 24
VCC = 1.5 V ± 0.1 V TA = 25°C 5.7 8.3 11.8
TA = –40°C to +85°C 4.6 15.9
VCC = 1.8 V ± 0.15 V TA = 25°C 4.7 6.7 9.6
TA = –40°C to +85°C 3.8 13
VCC = 2.5 V ± 0.2 V TA = 25°C 3.7 4.9 7
TA = –40°C to +85°C 2.9 9
VCC = 3.3 V ± 0.3 V TA = 25°C 3.2 4.1 5.8
TA = –40°C to +85°C 2.6 7.2

6.12 Operating Characteristics

TA = 25°C
PARAMETER TEST CONDITIONS VCC TYP UNIT
Cpd Power dissipation capacitance f = 10 MHz 0.8 V 2.5 pF
1.2 V ± 0.1 V 2.5
1.5 V ± 0.1 V 2.5
1.8 V ± 0.15 V 2.5
2.5 V ± 0.2 V 3
3.3 V ± 0.3 V 3

6.13 Typical Characteristics

SN74AUP1G79 D001_SCES604.gif Figure 1. TPD vs VCC
SN74AUP1G79 D002_SCES604.gif Figure 2. TPD vs Temperature

7 Parameter Measurement Information

7.1 Propagation Delays, Setup and Hold Times, and Pulse Width

SN74AUP1G79 pmi1_ces592.gif Figure 3. Load Circuit and Voltage Waveforms

7.2 Enable and Disable Times

SN74AUP1G79 pmi2_ces592.gif Figure 4. Load Circuit and Voltage Waveforms

8 Detailed Description

8.1 Overview

The SN74AUP1G79 is a single positive-edge-triggered D-type flip-flop. Data at the input (D) is transferred to the output (Q) on the positive-going edge of the clock pulse when the setup time requirement is met. Because the clock triggering occurs at a voltage level, it is not directly related to the rise time of the clock pulse. This allows for data at the input to be changed without affecting the level at the output, following the hold-time interval.

8.2 Functional Block Diagram

SN74AUP1G79 ld_ces592.gif Figure 5. Logic Diagram (Positive Logic)

8.3 Feature Description

8.3.1 Balanced CMOS Push-Pull Outputs

A balanced output allows the device to sink and source similar currents. The drive capability of this device may create fast edges into light loads so routing and load conditions should be considered to prevent ringing. Additionally, the outputs of this device are capable of driving larger currents than the device can sustain without being damaged. It is important for the power output of the device to be limited to avoid damage due to over-current. The electrical and thermal limits defined the in the Absolute Maximum Ratings must be followed at all times.

8.3.2 Standard CMOS Inputs

Standard CMOS inputs are high impedance and are typically modelled as a resistor in parallel with the input capacitance given in the Electrical Characteristics: TA = 25°C. The worst case resistance is calculated with the maximum input voltage, given in the Absolute Maximum Ratings, and the maximum input leakage current, given in the Electrical Characteristics: TA = 25°C, using ohm's law (R = V ÷ I).

Signals applied to the inputs need to have fast edge rates, as defined by Δt/Δv in Recommended Operating Conditions to avoid excessive currents and oscillations. If a slow or noisy input signal is required, a device with a Schmitt-trigger input should be used to condition the input signal prior to the standard CMOS input.

8.3.3 Clamp Diodes

The inputs and outputs to this device have negative clamping diodes.

CAUTION

Voltages beyond the values specified in the Absolute Maximum Ratings table can cause damage to the device. The input negative-voltage and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
SN74AUP1G79 SN74LVC1G79-ClampDiodes.gif Figure 6. Electrical Placement of Clamping Diodes for Each Input and Output

8.3.4 Partial Power Down (Ioff)

The inputs and outputs for this device enter a high-impedance state when the supply voltage is 0 V. The maximum leakage into or out of any input or output pin on the device is specified by Ioff in the Electrical Characteristics: TA = 25°C.

8.3.5 Over-voltage Tolerant Inputs

Input signals to this device can be driven above the supply voltage so long as they remain below the maximum input voltage value specified in the Absolute Maximum Ratings.

8.4 Device Functional Modes

Table 1 lists the functional modes of the SN74AUP1G79 device.

Table 1. Function Table

INPUTS OUTPUT
Q
CLK D
↑ H H
↑ L L
L or H X Q0

9 Applications, Implementation, and Layout

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

9.1 Application Information

A rotary quadrature encoder is a simple, infinitely-turning knob that outputs two out-of-phase square waves as it is turned and is often used in electronics as a method of human interface. One signal will lead the other in phase depending on which direction the knob is turned. The SN74AUP1G79 can be used to determine which direction the knob is being turned without the need for a microcontroller or other complex monitoring system by connecting the outputs of the knob to the D and CLK inputs of the SN74AUP1G79 as shown in Figure 7. It is important to note that the CLK input will control when the direction signal changes, as shown in Figure 8.

9.2 Typical Application

SN74AUP1G79 SN74AUP1G79_Application1.gif Figure 7. Typical Application Diagram
SN74AUP1G79 SN74AUP1G79_TimingDiagram1.gif Figure 8. Timing Diagram for Quadrature Encoder Application

9.2.1 Design Requirements

The SN74AUP1G79 device uses CMOS technology and has balanced output drive. Take care to avoid bus contention because it can drive currents that would exceed maximum limits.

9.2.2 Detailed Design Procedure

  1. Recommended Input conditions
    • Rise time and fall time specifications. See Δt/ΔV in Recommended Operating Conditions.
    • Specified high and low levels. See VIH and VIL in Recommended Operating Conditions.
    • Inputs are overvoltage tolerant, which allows them to go as high as 3.6 V at any valid VCC
  2. Recommended output conditions
    • Load currents must not exceed 20 mA on the output and 50 mA total for the part

9.2.3 Application Curves

SN74AUP1G79 fig1_ces604.gif
Figure 9. AUP – The Lowest-Power Family
SN74AUP1G79 fig2_ces604.gif
Figure 10. Excellent Signal Integrity

10 Power Supply Recommendations

The power supply can be any voltage between the minimum and maximum supply voltage rating located in the Recommended Operating Conditions table. A 0.1-µF bypass capacitor is recommended to be connected from the VCC terminal to GND to prevent power disturbance. To reject different frequencies of noise, use multiple bypass capacitors in parallel. Capacitors with values of 0.1 µF and 1 µF are commonly used in parallel. The bypass capacitor must be installed as close to the power terminal as possible for best results.

11 Layout

11.1 Layout Guidelines

Even low data rate digital signals can contain high-frequency signal components due to fast edge rates. When a printed-circuit board (PCB) trace turns a corner at a 90° angle, a reflection can occur. A reflection occurs primarily because of the change of width of the trace. At the apex of the turn, the trace width increases to 1.414 times the width. This increase upsets the transmission-line characteristics, especially the distributed capacitance and self–inductance of the trace which results in the reflection. Not all PCB traces can be straight and therefore some traces must turn corners. Figure 11 shows progressively better techniques of rounding corners. Only the last example (BEST) maintains constant trace width and minimizes reflections.

An example layout is given in Figure 12 for the DPW (X2SON-5) package. This example layout includes a 0402 (metric) capacitor and uses the measurements found in the example board layout appended to this end of this datasheet. A via of diameter 0.1 mm (3.973 mil) is placed directly in the center of the device. This via can be used to trace out the center pin connection through another board layer, or it can be left out of the layout

11.2 Layout Example

SN74AUP1G79 layout_scds357.gif Figure 11. Trace Example
SN74AUP1G79 sces218_dpw_layout.gif Figure 12. Example Layout With DPW (X2SON-5) Package

12 Device and Documentation Support

12.1 Documentation Support

12.1.1 Related Documentation

For related documentation see the following:

Implications of Slow or Floating CMOS Inputs

12.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

12.3 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

    TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers.
    Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.

12.4 Trademarks

NanoStar, E2E are trademarks of Texas Instruments.

All other trademarks are the property of their respective owners.

12.5 Electrostatic Discharge Caution

esds-image

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

12.6 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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