ZHCSHV1A March   2018  – May 2018 SN65LVDS93B-Q1

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用范围
  3. 3 说明
    1.     简化原理图
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 TTL Input Data
      2. 8.3.2 LVDS Output Data
    4. 8.4 Device Functional Modes
      1. 8.4.1 Input Clock Edge
      2. 8.4.2 Low Power Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Power Up Sequence
        2. 9.2.2.2 Signal Connectivity
        3. 9.2.2.3 PCB Routing
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Board Stackup
      2. 11.1.2 Power and Ground Planes
      3. 11.1.3 Traces, Vias, and Other PCB Components
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 商标
    2. 12.2 静电放电警告
    3. 12.3 接收文档更新通知
    4. 12.4 社区资源
    5. 12.5 术语表
  13. 13机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

6.6 Timing Requirements

PARAMETER MIN MAX UNIT
Input clock period, tc 7.4 100 ns
Input clock modulation with modulation frequency 30 kHz 8%
with modulation frequency 50 kHz 6%
High-level input clock pulse width duration, tw 0.4 tc 0.6 tc ns
Input signal transition time, tt 3 ns
Data set up time, D0 through D27 before CLKIN (See Figure 4) 2 ns
Data hold time, D0 through D27 after CLKIN 0.8 ns
SN65LVDS93B-Q1 load_seq_lls846.gifFigure 1. Typical SN65LVDS93B-Q1 Load and Shift Sequences
SN65LVDS93B-Q1 sch_diag_lls846.gifFigure 2. Equivalent Input and Output Schematic Diagrams