ZHCSHV8B
August 2009 – March 2015
SN65LVDS93A
PRODUCTION DATA.
1
特性
2
应用
3
说明
Device Images
使用分立式 LVDS TX 的 RGB 视频系统
4
修订历史记录
5
说明 (续)
6
Pin Configuration and Functions
Pin Functions - TSSOP
Pin Functions - BGA MICROSTAR
7
Specifications
7.1
Absolute Maximum Ratings
7.2
ESD Ratings
7.3
Recommended Operating Conditions
7.4
Thermal Information
7.5
Electrical Characteristics
7.6
Timing Requirements
7.7
Switching Characteristics
7.8
Typical Characteristics
8
Parameter Measurement Information
9
Detailed Description
9.1
Overview
9.2
Functional Block Diagram
9.3
Feature Description
9.3.1
TTL Input Data
9.3.2
LVDS Output Data
9.4
Device Functional Modes
9.4.1
Input Clock Edge
9.4.2
Low Power Mode
10
Application and Implementation
10.1
Application Information
10.2
Typical Application
10.2.1
Design Requirements
10.2.2
Detailed Design Procedure
10.2.2.1
Power
10.2.2.2
Signal Connectivity
10.2.2.3
PCB Routing
10.2.3
Application Curve
11
Power Supply Recommendations
12
Layout
12.1
Layout Guidelines
12.1.1
Board Stackup
12.1.2
Power and Ground Planes
12.1.3
Traces, Vias, and Other PCB Components
12.2
Layout Example
13
器件和文档支持
13.1
文档支持
13.1.1
相关文档
13.2
接收文档更新通知
13.3
社区资源
13.4
商标
13.5
静电放电警告
13.6
Glossary
14
机械、封装和可订购信息
封装选项
机械数据 (封装 | 引脚)
DGG|56
MPDS570
散热焊盘机械数据 (封装 | 引脚)
订购信息
zhcshv8b_oa
zhcshv8b_pm
8
Parameter Measurement Information
Figure 5.
Equivalent Input and Output Schematic Diagrams
All input timing is defined at IOVDD / 2 on an input signal with a 10% to 90% rise or fall time of less than 3 ns. CLKSEL = 0V.
Figure 6.
Setup and Hold Time Definition
Figure 7.
Test Load and Voltage Definitions for LVDS Outputs
The 16 grayscale test pattern test device power consumption for a typical display pattern.
Figure 8.
16 Grayscale Test Pattern
The worst-case test pattern produces nearly the maximum switching frequency for all of the LVDS outputs.
Figure 9.
Worst-Case Power Test Pattern
CLKOUT is shown with CLKSEL at high-level.
CLKIN polarity depends on CLKSEL input level.
Figure 10.
SN65LVDS93A Timing Definitions
Figure 11.
Output Clock Jitter Test Set Up
Figure 12.
Enable Time Waveforms
Figure 13.
Disable Time Waveforms