SLLS396G SEPTEMBER 1999 – December 2015 SN65LVDS104 , SN65LVDS105
PRODUCTION DATA.
请参考 PDF 数据表获取器件具体的封装图。
To minimize the power supply noise floor, provide good decoupling near the SN65LVDS10x power pins. It is recommended to place one 0.01-μF ceramic capacitor at each power pin, and two 0.1-μF ceramic capacitors on each power node. The distance between the device and capacitors must be minimized to reduce loop inductance and provide optimal noise filtering. Placing the capacitor underneath the device on the bottom of the PCB is often a good choice. A 100-pF ceramic capacitor can be put at each power pin to optimize the EMI performance.