SLLS236I October   1996  – June 2015 SN65LBC184 , SN75LBC184

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: Driver
    6. 6.6  Electrical Characteristics: Receiver
    7. 6.7  Driver Switching Characteristics
    8. 6.8  Receiver Switching Characteristics
    9. 6.9  Dissipation Ratings
    10. 6.10 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Data Rate and Bus Length
        2. 9.2.1.2 Stub Length
        3. 9.2.1.3 Bus Loading
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 SN65LBC184 Test Description
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Related Links
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

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11 Layout

11.1 Layout Guidelines

Because ESD transients have a wide frequency bandwidth from approximately 3 MHz to 3 GHz, high-frequency layout techniques must be applied during PCB design.

  • Use VCC and ground planes to provide low inductance. High frequency currents follow the path of least inductance and not the path of least impedance.
  • Apply 100-nF to 220-nF bypass capacitors as close as possible to the VCC pins of transceiver, UART, or controller ICs on the board.
  • Use at least two vias for VCC and ground connections of bypass capacitors to minimize effective via-inductance.
  • Use 1-kΩ to 10-kΩ pullup or pulldown resistors for enable lines to limit noise currents in these lines during transient events.

11.2 Layout Example

SN65LBC184 SN75LBC184 layout_example_slls236.gifFigure 21. Layout Schematic