SLAS638A January   2009  – October 2015 SN65HVS885

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Waveforms
    2. 7.2 Signal Conventions
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Digital Inputs
      2. 8.3.2 Debounce Filter
      3. 8.3.3 Shift Register
      4. 8.3.4 Temperature Sensor
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 System-Level EMC
      2. 9.1.2 Input Channel Switching Characteristics
      3. 9.1.3 Digital Interface Timing
      4. 9.1.4 Cascading for High Channel Count Input Modules
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Input Stage
        2. 9.2.2.2 Setting Debounce Time
        3. 9.2.2.3 Using the HOT Indicator
        4. 9.2.2.4 Example: High-Voltage Sensing Application
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Community Resources
    2. 12.2 Trademarks
    3. 12.3 Electrostatic Discharge Caution
    4. 12.4 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
VCC Device power input VCC –0.5 6 V
VIPx Field digital inputs IPx –0.3 36 V
VID Voltage at any logic input DB0, DB1, CLK, SIP, CE, LD –0.5 6 V
IO Output current HOT, SOP –8 8 mA
PTOT Continuous total power dissipation See Thermal Information
TJ Junction temperature 170 °C
Tstg Storage temperature 150 °C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) All pins ±4000 V
IPx ±15000
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1000
Machine model (MM)(3) ±100
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
(3) JEDEC Standard 22, Method A115-A

6.3 Recommended Operating Conditions

MIN NOM MAX UNIT
VCC Device supply voltage 4.5 5 5.5 V
VIPL Field input low-state input voltage 0 4 V
VIPH Field input high-state input voltage 5.5 34 V
VIL Logic low-state input voltage 0 0.8 V
VIH Logic high-state input voltage 2.0 5.5 V
RLIM Current limiter resistor 17 25 500 kΩ
fIP (1) Input data rate 0 1 Mbps
TA Device –40 125 °C
TJ Junction Temperature 150 °C
(1) Maximum data rate corresponds to 0 ms debounce time, (DB0 = open, DB1 = GND), and RIN = 0 Ω

6.4 Thermal Information

THERMAL METRIC(1) SN65HVS885 UNIT
PWP (HTSSOP)
28 PINS
RθJA Junction-to-ambient thermal resistance High-K thermal resistance 35 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 4.27 °C/W
RθJB Junction-to-board thermal resistance 15 °C/W
ψJT Junction-to-top characterization parameter 0.6 °C/W
ψJB Junction-to-board characterization parameter 15.9 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 2.4 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

over full-range of recommended operating conditions (unless otherwise noted) all voltages measured against device ground, see Figure 9
PARAMETER TERMINAL TEST CONDITIONS MIN TYP MAX UNIT
FIELD INPUTS
VTH–(IP) Low-level device input threshold voltage IP0–IP7 RLIM = 25 kΩ 4 4.3 V
VTH+(IP) High-level device input threshold voltage 5.2 5.5 V
VHYS(IP) Device input hysteresis 0.9 V
VTH–(IN) Low-level field input threshold voltage Measured at
field side of RIN 		4.5 V < VCC < 5.5 V,
RIN = 1.2 kΩ ± 5%,
RLIM = 25 kΩ, TA ≤ 125°C		 6 8.4 V
VTH+(IN) High-level field input threshold voltage 9.4 10 V
VHYS(IN) Field input hysteresis 1 V
RIP Input resistance IP0–IP7 3 V < VIPx < 6 V,
RLIM = 25 kΩ		 0.2 0.63 1.1 kΩ
IIP-LIM Input current limit IP0–IP7 RLIM = 25 kΩ 3.15 3.6 4 mA
tDB Debounce times of input channels IP0–IP7 DB0 = open, DB1 = GND 0 ms
DB0 = GND, DB1 = open 1
DB0 = DB1 = open 3
IRE-on RE on-state current RE0–RE7 RLIM = 25 kΩ, REX = GND 2.8 3.15 3.5 mA
DEVICE SUPPLY
ICC(VCC) Supply current VCC IP0 to IP7 = 24V, REX = GND,
All logic inputs open		 6.5 10 mA
LOGIC INPUTS AND OUTPUTS
VOL Logic low-level output voltage SOP, HOT IOL = 20 μA 0.4 V
VOH Logic high-level output voltage IOH = –20 μA 4 V
IIL Logic input leakage current DB0, DB1, SIP,
LD, CE, CLK		 –50 50 μA
TOVER Over-temperature indication 150 °C
TSHDN Shutdown temperature 170 °C
POWER DISSIPATION
PD Power Dissipation VCC = 5 V, RIN = 0Ω,
RLIM = 25 kΩ,
RE0 – RE7 = GND,
fCLK = 100 MHz		 IP0-IP7 = 34 V 1100 mW
IP0-IP7 = 24 V
IP0-IP7 = 20 V
IP0-IP7 = 12 V

6.6 Timing Requirements

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
tW1 CLK pulse width See Figure 6 4 ns
tW2 LD pulse width See Figure 4 6 ns
tSU1 SIP to CLK setup time See Figure 7 4 ns
tH1 SIP to CLK hold time See Figure 7 2 ns
tSU2 Falling edge to rising edge (CE to CLK) setup time See Figure 8 4 ns
tREC LD to CLK recovery time See Figure 5 2 ns
fCLK Clock pulse frequency See Figure 6 DC 100 MHz

6.7 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPLH1, tPHL1 CLK to SOP CL = 15 pF, see Figure 6 10 ns
tPLH2, tPHL2 LD to SOP CL = 15 pF, see Figure 4 14 ns
tr, tf Rise and fall times CL = 15 pF, see Figure 6 6 ns

6.8 Typical Characteristics

SN65HVS885 g_typinput_las638.gif Figure 1. Typical Input Characteristics
SN65HVS885 g_ilimeter_tj_las638.gif Figure 2. Typical Current Limiter Variation vs Ambient Temperature
SN65HVS885 g_vlimeter_tj_las638.gif Figure 3. Typical Limiter Threshold Voltage Variation vs Ambient Temperature