SLLS632C December   2005  – February 2015 SN65HVD1050

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (Continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Driver Electrical Characteristics
    6. 7.6  Receiver Electrical Characteristics
    7. 7.7  Device Switching Characteristics
    8. 7.8  Driver Switching Characteristics
    9. 7.9  Receiver Switching Characteristics
    10. 7.10 Supply Current
    11. 7.11 S-Pin Characteristics
    12. 7.12 VREF-Pin Characteristics
    13. 7.13 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Mode Control
        1. 9.3.1.1 Normal Mode
        2. 9.3.1.2 Silent Mode
      2. 9.3.2 TXD Dominant Timeout (DTO)
      3. 9.3.3 Thermal Shutdown
      4. 9.3.4 VREF
      5. 9.3.5 Operating Temperature Range
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
        1. 10.2.1.1 Bus Loading, Length, and Number of Nodes
        2. 10.2.1.2 CAN Termination
          1. 10.2.1.2.1 Loop Propagation Delay
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 ESD Protection
        2. 10.2.2.2 Transient Voltage Suppresser (TVS) Diodes
      3. 10.2.3 Application Curve
    3. 10.3 System Example
      1. 10.3.1 ISO 11898 Compliance of SN65HVD1050 5-V CAN Transceiver
        1. 10.3.1.1 Introduction
        2. 10.3.1.2 Differential Signal
        3. 10.3.1.3 Common-Mode Signal
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Trademarks
    2. 13.2 Electrostatic Discharge Caution
    3. 13.3 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

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7 Specifications

7.1 Absolute Maximum Ratings(1)

MIN MAX UNIT
VCC Supply voltage(2) –0.3 7 V
Voltage range at any bus terminal (CANH, CANL, Vref) –27 40 V
IO Receiver output current 20 mA
VI Voltage input, transient pulse(3) (CANH, CANL) –200 200 V
VI Voltage input range (TXD, S) –0.5 6 V
TJ Junction temperature –55 170 °C
Tstg Storage temperature –40 125 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
(3) Tested in accordance with ISO 7637, test pulses 1, 2, 3a, 3b, 5, 6, and 7.

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) All pins ±8000 V
Bus pins vs GND ±4000
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1500
Machine Model, ANSI/ESDS5.2-1996 ±200
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

MIN NOM MAX UNIT
VCC Supply voltage 4.5 5.5 V
VI or VIC Voltage at any bus terminal (separately or common mode) –12 12 V
VIH High-level input voltage TXD, S 2.1 VCC V
VIL Low-level input voltage 0 0.8 V
VID Differential input voltage –7 7 V
IOH High-level output current Driver –70 mA
Receiver –2
IOL Low-level output current Driver 70 mA
Receiver 2
TJ Junction temperature See Absolute Maximum Ratings, 1-Mbps minimum signaling rate with RL = 54 Ω –40 150 °C
Signaling Rate 20 kbps

7.4 Thermal Information

THERMAL METRIC(1) SN65HVD1050 UNIT
D (SOIC)
8 PINS
RθJA Junction-to-air, Low-K thermal resistance(2) 211 °C/W
Junction-to-air, High-K thermal resistance 131
RθJC(top) Junction-to-case (top) thermal resistance 79
RθJB Junction-to-board thermal resistance 53
ψJT Junction-to-top characterization parameter 10.3
ψJB Junction-to-board characterization parameter 56.6
RθJC(bot) Junction-to-case (bottom) thermal resistance 112
PD Average power dissipation, VCC = 5.0V, Tj = 27°C, RL = 60 Ω, S at 0V, Input to TXD a 500 kHz, 50% duty cycle square wave. CL at RXD = 15 pF 170 mW
Average power dissipation, VCC = 5.5V, Tj = 130°C, RL = 45 Ω, S at 0V, Input to TXD a 500 kHz, 50% duty cycle square wave. CL at RXD = 15 pF 170
TJ_shutdown Junction temperature, thermal shutdown(3) 190 °C
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) Tested in accordance with the Low-K or High-K thermal metric definitions of EIA/JESD51-3 for leaded surface-mount packages.
(3) Extended operation in thermal shutdown may affect device reliability, see APPLICATIONS INFORMATION.

7.5 Driver Electrical Characteristics

over recommended operating conditiions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT
VO(D) Bus output voltage (Dominant) CANH VI = 0V, S at 0V, RL = 60 Ω, See Figure 11 and Figure 12 4.75V < VCC < 5.25V 2.9 3.4 4.5 V
4.5V < VCC < 5.5V 2.75 5.2
CANL 4.75V < VCC < 5.25V 0.8 1.5
4.5V < VCC < 5.5V 1.6
VO(R) Bus output voltage (Recessive) VI = 3V, S at 0V, RL = 60 Ω, See Figure 11 and Figure 12 4.75V < VCC < 5.25V 2 2.3 3 V
4.5V < VCC < 5.5V 1.8 3
VOD(D) Differential output voltage (Dominant) VI = 0V, RL = 60 Ω, S at 0V, See Figure 11, Figure 12, and Figure 13 4.75V < VCC < 5.25V 1.5 3 V
4.5V < VCC < 5.5V 1.4 3
VI = 0V, RL = 45 Ω, S at 0V, See Figure 11, Figure 12, and Figure 13 4.75V < VCC < 5.25V 1.4 3
4.5V < VCC < 5.5V 1.3 3
VOD(R) Differential output voltage (Recessive) VI = 3V, S at 0V, See Figure 11 and Figure 12 –0.012 0.012 V
VI = 3V, S at 0V, No Load –0.5 0.05
VOC(ss) Steady state common-mode output voltage S at 0V, Figure 18 4.75V < VCC < 5.25V 2 2.3 3 V
4.5V < VCC < 5.5V 1.9 3
ΔVOC(ss) Change in steady-state common-mode output voltage 30 mV
IIH High-level input current, TXD input VI at VCC –2 2 μA
IIL Low-level input current, TXD input VI at 0V –50 –10
IO(off) Power-off TXD output current VCC at 0V, TXD at 5V 1
IOS(ss) Short-circuit steady-state output current VCANH = -12V, CANL Open, See Figure 21 –105 –72 mA
VCANH = 12V, CANL Open, SeeFigure 21 0.36 1
VCANL = -12V, CANH Open, See Figure 21 –1 –0.5
VCANL = 12V , CANH Open, See Figure 21 71 105
CO Output capacitance See receiver input capacitance
(1) All typical values are at 25°C with a 5-V supply.

7.6 Receiver Electrical Characteristics

over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT
VIT+ Positive-going input threshold voltage S at 0V, See Table 1 800 900 mV
VIT– Negative-going input threshold voltage 500 650
Vhys Hysteresis voltage (VIT+ – VIT–) 100 125
VOH High-level output voltage IO = –2 mA, See Figure 16 4.75V < VCC < 5.25V 4 4.6 V
4.5V < VCC < 5.5V 3.8
VOL Low-level output voltage IO = 2 mA, See Figure 16 0.2 0.4 V
II(off) Power-off bus input current CANH or CANL = 5V,
Other pin at 0V,
VCC at 0V, TXD at 0V		 165 250 μA
IO(off) Power-off RXD leakage current VCC at 0V, RXD at 5V 20 μA
CI Input capacitance to ground, (CANH or CANL) TXD at 3V,
VI = 0.4 sin (4E6πt) + 2.5V		 13 pF
CID Differential input capacitance TXD at 3V, VI = 0.4 sin (4E6πt) 5
RID Differential input resistance TXD at 3V, S at 0V 30 80 kΩ
RIN Input resistance, (CANH or CANL) 15 30 40
RI(m) Input resistance matching
[1 – (RIN (CANH) / RIN (CANL))] x 100%		 V(CANH) = V(CANL) –3% 0% 3%
(1) All typical values are at 25°C with a 5-V supply.

7.7 Device Switching Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
td(LOOP1) Total loop delay, driver input to receiver output, recessive to dominant Figure 19, S at 0V 4.75V < VCC < 5.25V 90 190 ns
4.5V < VCC < 5.5V 85 195
td(LOOP2) Total loop delay, driver input to receiver output, dominant to recessive 4.75V < VCC < 5.25V 90 190
4.5V < VCC < 5.5V 85 195

7.8 Driver Switching Characteristics

over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPLH Propagation delay time, low-to-high-level output S at 0V, See Figure 14 25 65 120 ns
tPHL Propagation delay time, high-to-low-level output 25 45 90
tr Differential output signal rise time 25
tf Differential output signal fall time 50
ten Enable time from silent mode to dominant See Figure 17 1 μs
t(dom) Dominant time-out ↓VI, See Figure 20 4.75V < VCC < 5.25V 300 450 700 μs
4.5V < VCC < 5.5V 280 700

7.9 Receiver Switching Characteristics

over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPLH Propagation delay time, low-to-high-level output S at 0V or VCC, See Figure 16 4.75V < VCC < 5.25V 60 100 130 ns
4.5V < VCC < 5.5V 60 135
tPHL Propagation delay time, high-to-low-level output 4.75V < VCC < 5.25V 45 70 90
4.5V < VCC < 5.5V 45 95
tr Output signal rise time 8
tf Output signal fall time 8

7.10 Supply Current

over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ICC 5-V Supply current Silent mode S at VCC, VI = VCC 6 10 mA
Dominant VI = 0V, 60 Ω Load, S at 0V 4.75V < VCC < 5.25V 50 70
4.5V < VCC < 5.5V 75
Recessive VI = VCC, No Load, S at 0V 6 10

7.11 S-Pin Characteristics

over recommended operating conditiions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IIH High level input current S at 2V 20 40 70 μA
IIL Low level input current S at 0.8V 5 20 30

7.12 VREF-Pin Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VREF Reference output voltage –50 μA < IO < 50 μA 0.4VCC 0.5VCC 0.6VCC V

7.13 Typical Characteristics

SN65HVD1050 rec_dom_ta_lls632.gif
Figure 1. Recessive-to-Dominant Loop Time vs Free-Air Temperature (Across VCC)
SN65HVD1050 icc_sr_lls632.gif
Figure 3. Supply Current (RMS) vs Signaling Rate
SN65HVD1050 ioh_vo_lls632.gif
Figure 5. Driver High-Level Output Voltage vs High-Level Output Current
SN65HVD1050 iod_vcc_lls632.gifFigure 7. Driver Output Current vs Supply Voltage
SN65HVD1050 typ_emis_lls632.gifFigure 9. Frequency Spectrum of Common-Mode Emissions
SN65HVD1050 dom_rec_ta_lls632.gif
Figure 2. Dominant-to-Recessive Loop Time vs Free-Air Temperature (Across VCC)
SN65HVD1050 iol_vo_lls632.gif
Figure 4. Driver Low-Level Output Voltage vs Low-Level Output Current
SN65HVD1050 ddd_vo_ta_lls632.gif
Figure 6. Driver Differential Output Voltage vs Free-Air Temperature (Across VCC)
SN65HVD1050 vor_vid_lls632.gifFigure 8. Receiver Output Voltage vs Differential Input Voltage
SN65HVD1050 elv_imm_iis632.gifFigure 10. Direct Power Injection (DPI) Response vs Frequency