ZHCSBP5C september   2013  – october 2020 SN65DSI86

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Revision History
  6. 5 Description (continued)
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 MIPI Dual DSI Interface
      2. 8.3.2 Embedded DisplayPort Interface
      3. 8.3.3 General-Purpose Input and Outputs
        1. 8.3.3.1 GPIO REFCLK and DSIA Clock Selection
        2. 8.3.3.2 Suspend Mode
        3. 8.3.3.3 Pulse Width Modulation (PWM)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Reset Implementation
      2. 8.4.2 Power-Up Sequence
      3. 8.4.3 Power Down Sequence
      4. 8.4.4 Display Serial Interface (DSI)
        1. 8.4.4.1 DSI Lane Merging
        2. 8.4.4.2 DSI Supported Data Types
        3. 8.4.4.3 Generic Request Datatypes
          1. 8.4.4.3.1 Generic Read Request 2-Parameters Request
          2. 8.4.4.3.2 Generic Short Write 2-Parameters Request
          3. 8.4.4.3.3 Generic Long Write Packet Request
        4. 8.4.4.4 DSI Pixel Stream Packets
        5. 8.4.4.5 DSI Video Transmission Specifications
        6. 8.4.4.6 Video Format Parameters
        7. 8.4.4.7 GPU LP-TX Clock Requirements
      5. 8.4.5 DisplayPort
        1. 8.4.5.1  HPD (Hot Plug/Unplug Detection)
        2. 8.4.5.2  AUX_CH
          1. 8.4.5.2.1 Native Aux Transactions
        3. 8.4.5.3  I2C-Over-AUX
          1. 8.4.5.3.1 Direct Method (Clock Stretching)
          2. 8.4.5.3.2 Indirect Method (CFR Read/Write)
        4. 8.4.5.4  DisplayPort PLL
        5. 8.4.5.5  DP Output VOD and Pre-emphasis Settings
        6. 8.4.5.6  DP Main Link Configurability
        7. 8.4.5.7  DP Main Link Training
          1. 8.4.5.7.1 Manual Link Training
          2. 8.4.5.7.2 Fast Link Training
          3. 8.4.5.7.3 54
          4. 8.4.5.7.4 Semi-Auto Link Training
          5. 8.4.5.7.5 Redriver Semi-Auto Link Training
        8. 8.4.5.8  Panel Size vs DP Configuration
        9. 8.4.5.9  Panel Self Refresh (PSR)
        10. 8.4.5.10 Secondary Data Packet (SDP)
        11. 8.4.5.11 Color Bar Generator
        12. 8.4.5.12 DP Pattern
          1. 8.4.5.12.1 HBR2 Compliance Eye
          2. 8.4.5.12.2 80-Bit Custom Pattern
        13. 8.4.5.13 BPP Conversion
    5. 8.5 Programming
      1. 8.5.1 Local I2C Interface Overview
    6. 8.6 Register Map
      1. 8.6.1 Standard CFR Registers (PAGE 0)
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 1080p (1920x1080 60 Hz) Panel
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 eDP Design Procedure
          2. 9.2.1.2.2 76
          3. 9.2.1.2.3 DSI Design Procedure
          4. 9.2.1.2.4 78
          5. 9.2.1.2.5 Example Script
        3. 9.2.1.3 Application Curve
  11. 10Power Supply Recommendations
    1. 10.1 VCC Power Supply
    2. 10.2 VCCA Power supply
    3. 10.3 VPLL and VCCIO Power Supplies
  12. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 DSI Guidelines
      2. 11.1.2 eDP Guidelines
      3. 11.1.3 Ground
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
  14. 13Mechanical, Packaging, and Orderable Information

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9.2.1.2.5 Example Script

This example configures the SN65DSI86 for the following configuration:

<aardvark>
<configure i2c="1" spi="1" gpio="0" tpower="1" pullups="0" /> 
<i2c_bitrate khz="100" /> 
======REFCLK 27MHz ====== 
<i2c_write addr="0x2D" count="1" radix="16">0A 06</i2c_write> /> 
======Single 4 DSI lanes====== 
<i2c_write addr="0x2D" count="1" radix="16">10 26</i2c_write> /> 
======DSIA CLK FREQ 445MHz====== 
<i2c_write addr="0x2D" count="1" radix="16">12 59</i2c_write> /> 
======enhanced framing and ASSR====== 
<i2c_write addr="0x2D" count="1" radix="16">5A 05</i2c_write> /> 
======2 DP lanes no SSC====== 
<i2c_write addr="0x2D" count="1" radix="16">93 20</i2c_write> /> 
======HBR (2.7Gbps)====== 
<i2c_write addr="0x2D" count="1" radix="16">94 80</i2c_write> /> 
======PLL ENABLE====== 
<i2c_write addr="0x2D" count="1" radix="16">0D 01</i2c_write> <sleep ms="10" /> 
======Verify PLL is locked====== 
<i2c_write addr="0x2D" count="0" radix="16">0A</i2c_write> /> 
<i2c_read addr="0x2D" count="2" radix="16">00</i2c_read> <sleep ms="10" /> 
======POST-Cursor2 0dB ====== 
<i2c_write addr="0x2D" count="1" radix="16">95 00</i2c_write> /> 
======Write DPCD Register 0x0010A in Sink to Enable ASSR====== 
<i2c_write addr="0x2D" count="1" radix="16">64 01</i2c_write> /> 
<i2c_write addr="0x2D" count="1" radix="16">74 00</i2c_write> /> 
<i2c_write addr="0x2D" count="1" radix="16">75 01</i2c_write> /> 
<i2c_write addr="0x2D" count="1" radix="16">76 0A</i2c_write> /> 
<i2c_write addr="0x2D" count="1" radix="16">77 01</i2c_write> /> 
<i2c_write addr="0x2D" count="1" radix="16">78 81</i2c_write> <sleep ms="10" /> 
======Semi-Auto TRAIN ====== 
<i2c_write addr="0x2D" count="1" radix="16">96 0A</i2c_write> <sleep ms="20" /> 
======Verify Training was successful====== 
<i2c_write addr="0x2D" count="0" radix="16">96</i2c_write> /> 
<i2c_read addr="0x2D" count="1" radix="16">00</i2c_read> <sleep ms="10" /> 
=====CHA_ACTIVE_LINE_LENGTH is 1920 ======= 
<i2c_write addr="0x2D" count="2" radix="16">20 80 07</i2c_write> /> 
=====CHA_VERTICAL_DISPLAY_SIZE is 1080 ======= 
<i2c_write addr="0x2D" count="2" radix="16">24 38 04</i2c_write> /> 
=====CHA_HSYNC_PULSE_WIDTH is 44 positive ======= 
<i2c_write addr="0x2D" count="2" radix="16">2C 2C 00</i2c_write> /> 
=====CHA_VSYNC_PULSE_WIDTH is 5 positive======= 
<i2c_write addr="0x2D" count="2" radix="16">30 05 80</i2c_write> /> 
=====CHA_HORIZONTAL_BACK_PORCH is 148======= 
<i2c_write addr="0x2D" count="1" radix="16">34 94</i2c_write> /> 
=====CHA_VERTICAL_BACK_PORCH is 36======= 
<i2c_write addr="0x2D" count="1" radix="16">36 24</i2c_write> /> 
=====CHA_HORIZONTAL_FRONT_PORCH is 88======= 
<i2c_write addr="0x2D" count="1" radix="16">38 58</i2c_write> /> 
=====CHA_VERTICAL_FRONT_PORCH is 4======= 
<i2c_write addr="0x2D" count="1" radix="16">3A 04</i2c_write> /> 
======DP- 24bpp====== 
<i2c_write addr="0x2D" count="1" radix="16">5B 00</i2c_write> /> 
=====COLOR BAR disabled======= 
<i2c_write addr="0x2D" count="1" radix="16">3C 00</i2c_write> /> 
======enhanced framing, ASSR, and Vstream enable====== 
<i2c_write addr="0x2D" count="1" radix="16">5A 0D</i2c_write> /> 
</aardvark>