ZHCSFS1A December 2016 – June 2018 SN65DSI84-Q1
PRODUCTION DATA.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DE_NEG_POLARITY | HS_NEG_POLARITY | VS_NEG_POLARITY | LVDS_LINK_CFG | CHA_24BPP_MODE | CHB_24BPP_MODE | CHA_24BPP_FORMAT1 | CHB_24BPP_FORMAT |
R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | DE_NEG_POLARITY | R/W | 0 | 0 – DE is positive polarity driven ‘1’ during active pixel transmission on LVDS (default)
1 – DE is negative polarity driven ‘0’ during active pixel transmission on LVDS |
6 | HS_NEG_POLARITY | R/W | 1 | 0 – HS is positive polarity driven ‘1’ during corresponding sync conditions
1 – HS is negative polarity driven ‘0’ during corresponding sync (default) |
5 | VS_NEG_POLARITY | R/W | 1 | 0 – VS is positive polarity driven ‘1’ during corresponding sync conditions
1 – VS is negative polarity driven ‘0’ during corresponding sync (default) |
4 | LVDS_LINK_CFG | R/W | 1 | 0 – LVDS Channel A and Channel B outputs enabled
When CSR 0x10.6:5 = ’00’ or ‘01’, the LVDS is in Dual-Link configuration When CSR 0x10.6:5 = ‘10’, the LVDS is in two Single-Link configuration 1 – LVDS Single-Link configuration; Channel A output enabled and Channel B output disabled (default) |
3 | CHA_24BPP_MODE | R/W | 0 | 0 – Force 18bpp; LVDS channel A lane 4 (A_Y3P/N) is disabled (default)
1 – Force 24bpp; LVDS channel A lane 4 (B_Y3P/N) is enabled |
2 | CHB_24BPP_MODE | R/W | 0 | CHB_24BPP_MODE
0 – Force 18bpp; LVDS channel B lane 4 (A_Y3P/N) is disabled (default) 1 – Force 24bpp; LVDS channel B lane 4 (B_Y3P/N) is enabled |
1 | CHA_24BPP_FORMAT1 | R/W | 0 | This field selects the 24bpp data format
0 – LVDS channel A lane A_Y3P/N transmits the 2 most significant bits (MSB) per color; Format 2 (default) 1 – LVDS channel B lane A_Y3P/N transmits the 2 least significant bits (LSB) per color; Format 1 Note1: This field must be ‘0’ when 18bpp data is received from DSI. Note2: If this field is set to ‘1’ and CHA_24BPP_MODE is ‘0’, the SN65DSI84-Q1 will convert 24bpp data to 18bpp data for transmission to an 18bpp panel. In this configuration, the SN65DSI84-Q1 will not transmit the 2 LSB per color on LVDS channel A, because LVDS channel A lane A_Y3P/N is disabled. |
0 | CHB_24BPP_FORMAT | R/W | 0 | This field selects the 24bpp data format
0 – LVDS channel B lane B_Y3P/N transmits the 2 most significant bits (MSB) per color; Format 2 (default) 1 – LVDS channel B lane B_Y3P/N transmits the 2 least significant bits (LSB) per color; Format 1 Note1: This field must be ‘0’ when 18bpp data is received from DSI. Note2: If this field is set to ‘1’ and CHB_24BPP_MODE is ‘0’, the SN65DSI84-Q1 will convert 24bpp data to 18bpp data for transmission to an 18bpp panel. In this configuration, the SN65DSI84-Q1 will not transmit the 2 LSB per color on LVDS channel B, because LVDS channel B lane B_Y3P/Nis disabled. |