ZHCSAT9I september   2012  – october 2020 SN65DSI83

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings #GUID-BDB96F65-5C5F-4805-AA4B-B71B15ADA38F/SLLSEB91839
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Clock Configurations and Multipliers
      2. 7.3.2 ULPS
      3. 7.3.3 LVDS Pattern Generation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Reset Implementation
      2. 7.4.2 Initialization Sequence
      3. 7.4.3 LVDS Output Formats
      4. 7.4.4 DSI Lane Merging
      5. 7.4.5 DSI Pixel Stream Packets
      6. 7.4.6 DSI Video Transmission Specifications
    5. 7.5 Programming
      1. 7.5.1 Local I2C Interface Overview
    6. 7.6 Register Maps
      1. 7.6.1 Control and Status Registers Overview
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Video STOP and Restart Sequence
      2. 8.1.2 Reverse LVDS Pin Order Option
      3. 8.1.3 IRQ Usage
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Example Script
      3. 8.2.3 Application Curve
  10. 9 Power Supply Recommendations
    1. 9.1 VCC Power Supply
    2. 9.2 VCORE Power Supply
  11. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Package Specific
      2. 10.1.2 Differential Pairs
      3. 10.1.3 Ground
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Community Resources
    3. 11.3 Trademarks
  13.   Mechanical, Packaging, and Orderable Information

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8.2.2.1 Example Script

This example configures the SN65DSI83 device for the following configuration:

<aardvark>
<configure i2c="1" spi="1" gpio="0" tpower="1" pullups="1"/>
<i2c_bitrate khz="100"/>
=====SOFTRESET=======
<i2c_write addr="0x2D" count="1" radix="16">09 01</i2c_write> <sleep ms="10"/>
======PLL_EN(bit 0) - Enable LAST after addr 0A and 0B configured======
<i2c_write addr="0x2D" count="1" radix="16">0D 00</i2c_write> <sleep ms="10"/>
======HS_CLK_SRC bit0===
======LVDS_CLK_Range bit 3:1======
<i2c_write addr="0x2D" count="1" radix="16"> 0A 05</i2c_write> <sleep ms="10"/>
======DSI_CLK_DIVIDER bit7:3=====
======RefCLK multiplier(bit1:0)======
======00 - LVDSclk=source clk, 01 - x2, 10 -x3, 11 - x4======
<i2c_write addr="0x2D" count="1" radix="16">0B 28</i2c_write> <sleep ms="10"/>
======DSI Ch Confg Left_Right Pixels(bit7 - 0 for A ODD, B EVEN, 1 for the other config)======
======DSI Ch Mode(bit6:5) 00 - Dual, 01 - single, 10 - two single =======
======SOT_ERR_TOL_DIS(bit0)=======
<i2c_write addr="0x2D" count="1" radix="16">10 26</i2c_write> <sleep ms="10"/>
====500M====
<i2c_write addr="0x2D" count="1" radix="16">12 64</i2c_write> <sleep ms="10"/>
======bit7: DE_Pol, bit6:HS_Pol, bit5:VS_Pol, bit4: LVDS Link Cfg, bit3:CHA 24bpp, bit2: CHB 24bpp, bit1: CHA 24bpp fmt1, bit0: CHB 24bpp fmt1======
<i2c_write addr="0x2D" count="1" radix="16">18 72</i2c_write> <sleep ms="10"/>
<i2c_write addr="0x2D" count="1" radix="16">19 00</i2c_write> <sleep ms="10"/>
======CHA_LINE_LENGTH_LOW========
<i2c_write addr="0x2D" count="1" radix="16">20 00</i2c_write> <sleep ms="10"/>
======CHA_LINE_LENGTH_HIGH========
<i2c_write addr="0x2D" count="1" radix="16">21 05</i2c_write> <sleep ms="10"/>
======CHA_VERTICAL_DISPLAY_SIZE_LOW========
<i2c_write addr="0x2D" count="1" radix="16">24 00</i2c_write> <sleep ms="10"/>
======CHA_VERTICAL_DISPLAY_SIZE_HIGH========
<i2c_write addr="0x2D" count="1" radix="16">25 04</i2c_write> <sleep ms="10"/>
======CHA_SYNC_DELAY_LOW========
<i2c_write addr="0x2D" count="1" radix="16">28 20</i2c_write> <sleep ms="10"/>
======CHA_SYNC_DELAY_HIGH========
<i2c_write addr="0x2D" count="1" radix="16">29 01</i2c_write> <sleep ms="10"/>
======CHA_HSYNC_PULSE_WIDTH_LOW========
<i2c_write addr="0x2D" count="1" radix="16">2C 80</i2c_write> <sleep ms="10"/>
======CHA_HSYNC_PULSE_WIDTH_HIGH========
<i2c_write addr="0x2D" count="1" radix="16">2D 00</i2c_write> <sleep ms="10"/>
======CHA_VSYNC_PULSE_WIDTH_LOW========
<i2c_write addr="0x2D" count="1" radix="16">30 07</i2c_write> <sleep ms="10"/>
======CHA_VSYNC_PULSE_WIDTH_HIGH========
<i2c_write addr="0x2D" count="1" radix="16">31 00</i2c_write> <sleep ms="10"/>
======CHA_HOR_BACK_PORCH========
<i2c_write addr="0x2D" count="1" radix="16">34 C0</i2c_write> <sleep ms="10"/>
======CHA_VER_BACK_PORCH========
<i2c_write addr="0x2D" count="1" radix="16">36 00</i2c_write> <sleep ms="10"/>
======CHA_HOR_FRONT_PORCH========
<i2c_write addr="0x2D" count="1" radix="16">38 00</i2c_write> <sleep ms="10"/>
======CHA_VER_FRONT_PORCH========
<i2c_write addr="0x2D" count="1" radix="16">3A 00</i2c_write> <sleep ms="10"/>
======CHA/CHB TEST PATTERN(bit4 CHA, bit0 CHB)========
<i2c_write addr="0x2D" count="1" radix="16">3C 00</i2c_write> <sleep ms="10"/>
======PLL_EN(bit 0) - Enable LAST after addr 0A and 0B configured======
<i2c_write addr="0x2D" count="1" radix="16">0D 01</i2c_write> <sleep ms="10"/>
======Read======
<i2c_write addr="0x2D" count="1" radix="16">00</i2c_write> <sleep ms="10"/>
======Read======
<i2c_write addr="0x2D" count="256" radix="16">00</i2c_write> <sleep ms="10"/>
</aardvark>