ZHCSAT9I september 2012 – october 2020 SN65DSI83
PRODUCTION DATA
Many of the SN65DSI83 device functions are controlled by the control and status registers (CSR). All CSR registers are accessible through the local I2C interface.
See Table 7-4 through Table 7-9 for the SN65DSI83 CSR descriptions. Reserved or undefined bit fields must not be modified. Otherwise, the device may operate incorrectly.
| ADDRESS | BIT | DESCRIPTION | DEFAULT | ACCESS(1) |
|---|---|---|---|---|
| 0x00 – 0x08 | 7:0 | Reserved Addresses 0x08 – 0x00 = {0x01, 0x20, 0x20, 0x20, 0x44, 0x53, 0x49, 0x38, 0x35} | Reserved | R/O |
| ADDRESS | BIT | DESCRIPTION | DEFAULT | ACCESS (1) |
|---|---|---|---|---|
| 0x09 | 0 | SOFT_RESET This bit automatically clears when set to 1 and returns 0s when read. This bit must be set after the CSR’s are updated. This bit must also be set after making any changes to the DIS clock rate or after changing between DSI burst and nonburst modes. 0 – No action (default) 1 – Reset device to default condition excluding the CSR bits | 0 | W/O |
| 0x0A | 7 | PLL_EN_STAT After PLL_EN_STAT = 1, wait at least 3 ms for PLL to lock 0 – PLL not enabled (default) 1 – PLL enabled | 0 | R/O |
| 3:1 | LVDS_CLK_RANGE This field selects the frequency range of the LVDS output clock. 000 – 25 MHz ≤ LVDS_CLK < 37.5 MHz 001 – 37.5 MHz ≤ LVDS_CLK < 62.5 MHz 010 – 62.5 MHz ≤ LVDS_CLK < 87.5 MHz 011 – 87.5 MHz ≤ LVDS_CLK < 112.5 MHz 100 – 112.5 MHz ≤ LVDS_CLK < 137.5 MHz 101 – 137.5 MHz ≤ LVDS_CLK ≤ 154 MHz (default) 110 – Reserved 111 – Reserved | 101 | R/W | |
| 0 | HS_CLK_SRC 0 – LVDS pixel clock derived from input REFCLK (default) 1 – LVDS pixel clock derived from MIPI D-PHY channel A HS continuous clock | 0 | R/W | |
| 0x0B | 7:3 | DSI_CLK_DIVIDER When CSR 0x0A.0 = 1, this field controls the divider used to generate the LVDS output clock from the MIPI D-PHY Channel A HS continuous clock. When CSR 0x0A.0 = 0, this field must be programmed to 00000. 00000 – LVDS clock = source clock (default) 00001 – Divide by 2 00010 – Divide by 3 00011 – Divide by 4 … 10111 – Divide by 24 11000 – Divide by 25 11001 through 11111 – Reserved | 00000 | R/W |
| 1:0 | REFCLK_MULTIPLIER When CSR 0x0A.0 = 0, this field controls the multiplier used to generate the LVDS output clock from the input REFCLK. When CSR 0x0A.0 = 1, this field must be programmed to 00. 00 – LVDS clock = source clock (default) 01 – Multiply by 2 10 – Multiply by 3 11 – Multiply by 4 | 00 | R/W | |
| 0x0D | 0 | PLL_EN When this bit is set, the PLL is enabled with the settings programmed into CSR 0x0A and CSR 0x0B. The PLL must be disabled before changing any of the settings in CSR 0x0A and CSR 0x0B. The input clock source must be active and stable before the PLL is enabled. 0 – PLL disabled (default) 1 – PLL enabled | 0 | R/W |
| ADDRESS | BIT | DESCRIPTION | DEFAULT | ACCESS (1) |
|---|---|---|---|---|
| 0x10 | 7 | Reserved. Do not write to this field. Must remain at default. | 0 | R/W |
| 6:5 | Reserved. Do not write to this field. Must remain at default. | 01 | R/W | |
| 4:3 | CHA_DSI_LANES This field controls the number of lanes that are enabled for DSI channel A. 00 – Four lanes are enabled 01 – Three lanes are enabled 10 – Two lanes are enabled 11 – One lane is enabled (default) Note: Unused DSI input pins on the SN65DSI83 must be left unconnected. | 11 | R/W | |
| 0 | SOT_ERR_TOL_DIS 0 – Single bit errors are tolerated for the start of transaction SoT leader sequence (default) 1 – No SoT bit errors are tolerated | 0 | R/W | |
| 0x11 | 7:6 | CHA_DSI_DATA_EQ This field controls the equalization for the DSI channel A data lanes 00 – No equalization (default) 01 – 1 dB equalization 10 – Reserved 11 – 2 dB equalization | 00 | R/W |
| 3:2 | CHA_DSI_CLK_EQ This field controls the equalization for the DSI channel A clock 00 – No equalization (default) 01 – 1-dB equalization 10 – Reserved 11 – 2-dB equalization | 00 | R/W | |
| 0x12 | 7:0 | CHA_DSI_CLK_RANGE This field specifies the DSI clock frequency range in 5-MHz increments for the DSI channel A clock 0x00 through 0x07 – Reserved 0x08 – 40 ≤ frequency < 45 MHz 0x09 – 45 ≤ frequency < 50 MHz … 0x63 – 495 ≤ frequency < 500 MHz 0x64 – 500 MHz 0x65 through 0xFF – Reserved | 0 | R/W |
| ADDRESS | BIT | DESCRIPTION | DEFAULT | ACCESS (1) |
|---|---|---|---|---|
| 0x18 | 7 | DE_NEG_POLARITY 0 – DE is positive polarity driven 1 during active pixel transmission on LVDS (default) 1 – DE is negative polarity driven 0 during active pixel transmission on LVDS | 0 | R/W |
| 6 | HS_NEG_POLARITY 0 – HS is positive polarity driven 1 during corresponding sync conditions 1 – HS is negative polarity driven 0 during corresponding sync (default) | 1 | R/W | |
| 5 | VS_NEG_POLARITY 0 – VS is positive polarity driven 1 during corresponding sync conditions 1 – VS is negative polarity driven 0 during corresponding sync (default) | 1 | R/W | |
| 4 | Reserved. Do not write to this field. Must remain at default. | 1 | R/W | |
| 3 | CHA_24BPP_MODE 0 – Force 18 bpp; LVDS channel A lane 4 (A_Y3P or A_Y3N) is disabled (default) 1 – Force 24 bpp; LVDS channel A lane 4 (A_Y3P or A_Y3N) is enabled | 0 | R/W | |
| 1 | CHA_24BPP_FORMAT1 This field selects the 24 bpp data format 0 – LVDS channel A lane A_Y3P or A_Y3N transmits the 2 MSB per color; format 2 (default) 1 – LVDS channel A lane A_Y3P or A_Y3N transmits the 2 LSB per color; format 1 Note1: This field must be 0 when 18bpp data is received from DSI. Note2: If this field is set to 1 and CHA_24BPP_MODE is 0, the SN65DSI83 device will convert 24-bpp data to 18-bpp data for transmission to an 18-bpp panel. In this configuration, the SN65DSI83 device will not transmit the 2 LSB per color on LVDS channel A, since LVDS channel A lane 4 is disabled. | 0 | R/W | |
| 0x19 | 6 | CHA_LVDS_VOCM This field controls the common mode output voltage for LVDS channel A 0 – 1.2 V (default) 1 – 0.9 V (CSR 0x1B.5:4 CHA_LVDS_CM_ADJUST must be set to 01b) | 0 | R/W |
| 3:2 | CHA_LVDS_VOD_SWING This field controls the differential output voltage for LVDS channel A. See the Electrical Characteristics table for |VOD| for each setting: 00, 01 (default), 10, 11 | 01 | R/W | |
| 0x1A | 5 | CHA_REVERSE_LVDS This bit controls the order of the LVDS pins for channel A. 0 – Normal LVDS channel A pin order. LVDS channel A pin order is the same as listed in the Pin Assignments Section. (default) 1 – Reversed LVDS channel A pin order. LVDS channel A pin order is remapped as follows:
| 0 | R/W |
| 1 | CHA_LVDS_TERM This bit controls the near end differential termination for LVDS channel A. This bit also affects the output voltage for LVDS Channel A. 0 – 100-Ω differential termination 1 – 200-Ω differential termination (default) | 1 | R/W | |
| 0x1B | 5:4 | CHA_LVDS_CM_ADJUST This field can be used to adjust the common mode output voltage for LVDS channel A. 00 – No change to common mode voltage (default) 01 – Adjust common mode voltage down 3% 10 – Adjust common mode voltage up 3% 11 – Adjust common mode voltage up 6% | 00 | R/W |
For all video registers:
TEST PATTERN GENERATION PURPOSE ONLY registers are for test pattern generation use only. Others are for normal operation unless the test pattern generation feature is enabled.
| ADDRESS | BIT | DESCRIPTION | DEFAULT | ACCESS (1) |
|---|---|---|---|---|
| 0x20 | 7:0 | CHA_ACTIVE_LINE_LENGTH_LOW This field controls the length in pixels of the active horizontal line that are received on DSI channel A and output to LVDS channel A.. The value in this field is the lower 8 bits of the 12-bit value for the horizontal line length. | 0 | R/W |
| 0x21 | 3:0 | CHA_ACTIVE_LINE_LENGTH_HIGH This field controls the length in pixels of the active horizontal line that are received on DSI channel A and output to LVDS channel A.. The value in this field is the upper 4 bits of the 12-bit value for the horizontal line length. | 0 | R/W |
| 0x24 | 7:0 | CHA_VERTICAL_DISPLAY_SIZE_LOW TEST PATTERN GENERATION PURPOSE ONLY. This field controls the vertical display size in lines for LVDS channel A. The value in this field is the lower 8 bits of the 12-bit value for the vertical display size. The value in this field is only used for channel A test pattern generation. | 0 | R/W |
| 0x25 | 3:0 | CHA_VERTICAL_DISPLAY_SIZE_HIGH TEST PATTERN GENERATION PURPOSE ONLY. This field controls the vertical display size in lines for LVDS channel A. The value in this field is the upper 4 bits of the 12-bit value for the vertical display size. The value in this field is only used for channel A test pattern generation. | 0 | R/W |
| 0x28 | 7:0 | CHA_SYNC_DELAY_LOW This field controls the delay in pixel clocks from when an HSync or VSync is received on the DSI to when it is transmitted on the LVDS interface for channel A. The delay specified by this field is in addition to the pipeline and synchronization delays in the SN65DSI83 device. The additional delay is approximately 10 pixel clocks. The sync delay must be programmed to at least 32 pixel clocks to ensure proper operation. The value in this field is the lower 8 bits of the 12-bit value for the sync delay. | 0 | R/W |
| 0x29 | 3:0 | CHA_SYNC_DELAY_HIGH This field controls the delay in pixel clocks from when an HSync or VSync is received on the DSI to when it is transmitted on the LVDS interface for channel A. The delay specified by this field is in addition to the pipeline and synchronization delays in the SN65DSI83 device. The additional delay is approximately 10 pixel clocks. The sync delay must be programmed to at least 32 pixel clocks to ensure proper operation. The value in this field is the lower 4 bits of the 12-bit value for the sync delay. | 0 | R/W |
| 0x2C | 7:0 | CHA_HSYNC_PULSE_WIDTH_LOW This field controls the width in pixel clocks of the HSync pulse duration for LVDS channel A. The value in this field is the lower 8 bits of the 10-bit value for the HSync pulse duration. The value in this field is used for channel A test pattern generation when test pattern generation feature is enabled by programming bit 4 at 0x3C. | 0 | R/W |
| 0x2D | 1:0 | CHA_HSYNC_PULSE_WIDTH_HIGH This field controls the width in pixel clocks of the HSync pulse duration for LVDS channel A. The value in this field is the upper 2 bits of the 10-bit value for the HSync pulse duration. The value in this field is used for channel A test pattern generation when test pattern generation feature is enabled by programming bit 4 at 0x3C. | 0 | R/W |
| 0x30 | 7:0 | CHA_VSYNC_PULSE_WIDTH_LOW This field controls the length in lines of the VSync pulse duration for LVDS channel A. The value in this field is the lower 8 bits of the 10-bit value for the VSync pulse duration. The value in this field is used for channel A test pattern generation when test pattern generation feature is enabled by programming bit 4 at 0x3C. | 0 | R/W |
| 0x31 | 1:0 | CHA_VSYNC_PULSE_WIDTH_HIGH This field controls the length in lines of the VSync pulse duration for LVDS channel A. The value in this field is the upper 2 bits of the 10-bit value for the VSync pulse duration. The value in this field is used for channel A test pattern generation when test pattern generation feature is enabled by programming bit 4 at 0x3C. | 0 | R/W |
| 0x34 | 7:0 | CHA_HORIZONTAL_BACK_PORCH This field controls the time in pixel clocks between the end of the HSync pulse and the start of the active video data for LVDS channel A. The value in this field is used for channel A test pattern generation when test pattern generation feature is enabled by programming bit 4 at 0x3C. | 0 | R/W |
| 0x36 | 7:0 | CHA_VERTICAL_BACK_PORCH TEST PATTERN GENERATION PURPOSE ONLY. This field controls the number of lines between the end of the VSync pulse and the start of the active video data for LVDS channel A. The value in this field is only used for channel A test pattern generation. | 0 | R/W |
| 0x38 | 7:0 | CHA_HORIZONTAL_FRONT_PORCH TEST PATTERN GENERATION PURPOSE ONLY. This field controls the time in pixel clocks between the end of the active video data and the start of the HSync pulse for LVDS channel A. The value in this field is only used for channel A test pattern generation. | 0 | R/W |
| 0x3A | 7:0 | CHA_VERTICAL_FRONT_PORCH TEST PATTERN GENERATION PURPOSE ONLY. This field controls the number of lines between the end of the active video data and the start of the VSync pulse for LVDS channel A. The value in this field is only used for channel A test pattern generation. | 0 | R/W |
| 0x3C | 4 | CHA_TEST_PATTERN TEST PATTERN GENERATION PURPOSE ONLY. When this bit is set, the SN65DSI83 device will generate a video test pattern for LVDS channel A based on the values programmed into the video registers for channel A. | 0 | R/W |
| ADDRESS | BIT | DESCRIPTION | DEFAULT | ACCESS (1) |
|---|---|---|---|---|
| 0xE0 | 0 | IRQ_EN When enabled by this field, the IRQ output is driven high to communicate IRQ events. 0 – IRQ output is high-impedance (default) 1 – IRQ output is driven high when a bit is set in registers 0xE5 that also has the corresponding IRQ_EN bit set to enable the interrupt condition | 0 | R/W |
| 0xE1 | 7 | CHA_SYNCH_ERR_EN 0 – CHA_SYNCH_ERR is masked 1 – CHA_SYNCH_ERR is enabled to generate IRQ events | 0 | R/W |
| 6 | CHA_CRC_ERR_EN 0 – CHA_CRC_ERR is masked 1 – CHA_CRC_ERR is enabled to generate IRQ events | 0 | R/W | |
| 5 | CHA_UNC_ECC_ERR_EN 0 – CHA_UNC_ECC_ERR is masked 1 – CHA_UNC_ECC_ERR is enabled to generate IRQ events | 0 | R/W | |
| 4 | CHA_COR_ECC_ERR_EN 0 – CHA_COR_ECC_ERR is masked 1 – CHA_COR_ECC_ERR is enabled to generate IRQ events | 0 | R/W | |
| 3 | CHA_LLP_ERR_EN 0 – CHA_LLP_ERR is masked 1 – CHA_ LLP_ERR is enabled to generate IRQ events | 0 | R/W | |
| 2 | CHA_SOT_BIT_ERR_EN 0 – CHA_SOT_BIT_ERR is masked 1 – CHA_SOT_BIT_ERR is enabled to generate IRQ events | 0 | R/W | |
| 0 | PLL_UNLOCK_EN 0 – PLL_UNLOCK is masked 1 – PLL_UNLOCK is enabled to generate IRQ events | 0 | R/W | |
| 0xE5 | 7 | CHA_SYNCH_ERR When the DSI channel A packet processor detects an HS or VS synchronization error, that is, an unexpected sync packet; this bit is set; this bit is cleared by writing a 1 value. | 0 | R/W1C |
| 6 | CHA_CRC_ERR When the DSI channel A packet processor detects a data stream CRC error, this bit is set; this bit is cleared by writing a 1 value. | 0 | R/W1C | |
| 5 | CHA_UNC_ECC_ERR When the DSI channel A packet processor detects an uncorrectable ECC error, this bit is set; this bit is cleared by writing a 1 value. | 0 | R/W1C | |
| 4 | CHA_COR_ECC_ERR When the DSI channel A packet processor detects a correctable ECC error, this bit is set; this bit is cleared by writing a 1 value. | 0 | R/W1C | |
| 3 | CHA_LLP_ERR When the DSI channel A packet processor detects a low level protocol error, this bit is set; this bit is cleared by writing a 1 value. Low-level protocol errors include SoT and EoT sync errors, Escape Mode entry command errors, LP transmission sync errors, and false control errors. Lane merge errors are reported by this status condition. | 0 | R/W1C | |
| 2 | CHA_SOT_BIT_ERR When the DSI channel A packet processor detects an SoT leader sequence bit error, this bit is set; this bit is cleared by writing a 1 value. | 0 | R/W1C | |
| 0 | PLL_UNLOCK This bit is set whenever the PLL Lock status transitions from LOCK to UNLOCK. | 1 | R/W1C |