ZHCSAT9I september   2012  – october 2020 SN65DSI83

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings #GUID-BDB96F65-5C5F-4805-AA4B-B71B15ADA38F/SLLSEB91839
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Clock Configurations and Multipliers
      2. 7.3.2 ULPS
      3. 7.3.3 LVDS Pattern Generation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Reset Implementation
      2. 7.4.2 Initialization Sequence
      3. 7.4.3 LVDS Output Formats
      4. 7.4.4 DSI Lane Merging
      5. 7.4.5 DSI Pixel Stream Packets
      6. 7.4.6 DSI Video Transmission Specifications
    5. 7.5 Programming
      1. 7.5.1 Local I2C Interface Overview
    6. 7.6 Register Maps
      1. 7.6.1 Control and Status Registers Overview
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Video STOP and Restart Sequence
      2. 8.1.2 Reverse LVDS Pin Order Option
      3. 8.1.3 IRQ Usage
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Example Script
      3. 8.2.3 Application Curve
  10. 9 Power Supply Recommendations
    1. 9.1 VCC Power Supply
    2. 9.2 VCORE Power Supply
  11. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Package Specific
      2. 10.1.2 Differential Pairs
      3. 10.1.3 Ground
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Community Resources
    3. 11.3 Trademarks
  13.   Mechanical, Packaging, and Orderable Information

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5 Pin Configuration and Functions

GUID-1A318DDF-3672-4687-B12A-0DF59F39EEFD-low.svg ZXH Package64-Pin nFBGA(Top View)
Table 5-1 Pin Functions
PIN I/O DESCRIPTION
NAME NO.
A_CLKN F9 LVDS output FlatLink Channel A LVDS clock
A_CLKP F8
ADDR A1 CMOS I/O Local I2C Interface Target Address Select. See Table 7-3. In normal operation, this pin is an input. When the ADDR pin is programmed high, it must be tied to the same 1.8-V power rails where the SN65DSI83 VCC 1.8-V power rail is connected.
A_Y0N C9 LVDS output FlatLink Channel A LVDS data output 0
A_Y0P C8
A_Y1N D9 FlatLink Channel A LVDS data output 1
A_Y1P D8
A_Y2N E9 FlatLink Channel A LVDS data output 2
A_Y2P E8
A_Y3N G9 FlatLink Channel A LVDS data output 3. A_Y3P and A_Y3N shall be left NC for 18 bpp panels
A_Y3P G8
DA0N J3 LVDS Input (HS)
CMOS Input (LS)
(failsafe)		 MIPI D-PHY Channel A Data Lane 0; data rate up to 1 Gbps
DA0P H3
DA1N J4 MIPI D-PHY Channel A Data Lane 1; data rate up to 1 Gbps
DA1P H4
DA2N J6 MIPI D-PHY Channel A Data Lane 2; data rate up to 1 Gbps
DA2P H6
DA3N J7 MIPI D-PHY Channel A Data Lane 3; data rate up to 1 Gbps
DA3P H7
DACN J5 MIPI D-PHY Channel A Clock Lane; operates up to 500 MHz
DACP H5
EN B1 CMOS Input with pullup (failsafe) Chip enable and reset. Device is reset (shutdown) when EN is low.
GND A2, A8, B9, D5, E4, F4, F5, H9 Power Supply Reference ground
IRQ J9 CMOS Output Interrupt signal
NC B3, A3, B4, A4, B5, A5, B6, A6, B7, A7, C2, C1, D2, D1, F2, F1, G2, G1, E2, E1 No connects These pins must not be connected to any signal, power or ground.
REFCLK H2 CMOS Input (Failsafe) Optional external reference clock for LVDS pixel clock. If an external reference clock is not used, this pin must be pulled to GND with an external resistor. The source of the reference clock must be placed as close as possible with a series resistor near the source to reduce EMI.
RSVD1 H8 CMOS Input/Output with pulldown Reserved. This pin must be left unconnected for normal operation.
RSVD2 B2 CMOS Input with pulldown Reserved. This pin must be left unconnected for normal operation.
SCL H1 CMOS Input (Failsafe) Local I2C interface clock
SDA J1 Open Drain I/O (failsafe) Local I2C interface bidirectional data signal
VCC A9, B8, D6, E5, E6, F6, J2 Power Supply 1.8-V power supply
VCORE J8 1.1-V output from voltage regulator. This pin must have a 1-µF external capacitor to GND.