ZHCSIR4Q July   1995  – September 2018 SN54LVCH245A , SN74LVCH245A

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      简化原理图
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
    2.     Pin Assignments: ZQN Package
    3.     Pin Assignments: ZXY Package
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions: SN74LVCH245A
    4. 6.4  Recommended Operating Conditions: SN54LVCH245A
    5. 6.5  Thermal Information
    6. 6.6  Electrical Characteristics: SN74LVCH245A
    7. 6.7  Electrical Characteristics: SN54LVCH245A
    8. 6.8  Switching Characteristics: SN74LVCH245A, –40°C TO 85°C
    9. 6.9  Switching Characteristics: SN74LVCH245A, –40°C TO 125°C
    10. 6.10 Switching Characteristics: SN54LVCH245A
    11. 6.11 Operating Characteristics
    12. 6.12 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Balanced High-Drive CMOS Push-Pull Outputs
      2. 8.3.2 Standard CMOS Inputs
      3. 8.3.3 Negative Clamping Diodes
      4. 8.3.4 Bus-Hold Data Inputs
      5. 8.3.5 Partial Power Down (Ioff)
      6. 8.3.6 Over-voltage Tolerant Inputs
      7. 8.3.7 Output Enable
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 相关链接
    2. 12.2 商标
    3. 12.3 静电放电警告
    4. 12.4 术语表
  13. 13机械、封装和可订购信息

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • W|20
  • J|20
  • FK|20
散热焊盘机械数据 (封装 | 引脚)
订购信息

8.3.4 Bus-Hold Data Inputs

Each data input on this device includes a weak latch that maintains a valid logic level on the input. The state of these latches is unknown at startup and remains unknown until the input has been forced to a valid high or low state. After data has been sent through a channel, the latch then maintains the previous state on the input if the line is left floating.

NOTE

It is highly recommended to not use pull-up or pull-down resistors together with a bus-hold input.

Bus-hold data inputs prevent floating inputs on this device. The Implications of Slow or Floating CMOS Inputs application report explains the problems associated with leaving CMOS inputs floating.

These latches remain active at all times, independent of output disable signals such as direction selection or output enables.

The Bus-Hold Circuit application report has additional details regarding bus-hold inputs.

SN54LVCH245A SN74LVCH245A feat-bus-hold.gifFigure 9. Simplified Schematic For Device With Bus-Hold Data Inputs