SPNS229C October   2014  – November 2016 RM44L520 , RM44L920

PRODUCTION DATA.  

  1. Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. Revision History
  3. Device Comparison
    1. 3.1 Related Products
  4. Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
      1. 4.1.1 PGE QFP Package Pinout (144-Pin)
      2. 4.1.2 PZ QFP Package Pinout (100-Pin)
    2. 4.2 Signal Descriptions
      1. 4.2.1 PGE Package Terminal Functions
        1. 4.2.1.1  Multibuffered Analog-to-Digital Converters (MibADCs)
        2. 4.2.1.2  Enhanced High-End Timer (N2HET) Modules
        3. 4.2.1.3  Enhanced Capture Modules (eCAP)
        4. 4.2.1.4  Enhanced Quadrature Encoder Pulse Modules (eQEP)
        5. 4.2.1.5  Enhanced Pulse-Width Modulator Modules (ePWM)
        6. 4.2.1.6  General-Purpose Input/Output (GIO)
        7. 4.2.1.7  Controller Area Network Controllers (DCAN)
        8. 4.2.1.8  Local Interconnect Network Interface Module (LIN)
        9. 4.2.1.9  Standard Serial Communication Interface (SCI)
        10. 4.2.1.10 Inter-Integrated Circuit Interface Module (I2C)
        11. 4.2.1.11 Standard Serial Peripheral Interface (SPI)
        12. 4.2.1.12 Multibuffered Serial Peripheral Interface Modules (MibSPI)
        13. 4.2.1.13 System Module Interface
        14. 4.2.1.14 Clock Inputs and Outputs
        15. 4.2.1.15 Test and Debug Modules Interface
        16. 4.2.1.16 Flash Supply and Test Pads
        17. 4.2.1.17 Supply for Core Logic: 1.2V nominal
        18. 4.2.1.18 Supply for I/O Cells: 3.3V nominal
        19. 4.2.1.19 Ground Reference for All Supplies Except VCCAD
      2. 4.2.2 PZ Package Terminal Functions
        1. 4.2.2.1  High-End Timer (N2HET) Modules
        2. 4.2.2.2  Enhanced Capture Modules (eCAP)
        3. 4.2.2.3  Enhanced Quadrature Encoder Pulse Modules (eQEP)
        4. 4.2.2.4  Enhanced Pulse-Width Modulator Modules (ePWM)
        5. 4.2.2.5  General-Purpose Input/Output (GIO)
        6. 4.2.2.6  Controller Area Network Interface Modules (DCAN1, DCAN2)
        7. 4.2.2.7  Standard Serial Peripheral Interfaces (SPI2 and SPI4)
        8. 4.2.2.8  Multibuffered Serial Peripheral Interface (MibSPI1 and MibSPI3)
        9. 4.2.2.9  Local Interconnect Network Controller (LIN)
        10. 4.2.2.10 Multibuffered Analog-to-Digital Converter (MibADC)
        11. 4.2.2.11 System Module Interface
        12. 4.2.2.12 Clock Inputs and Outputs
        13. 4.2.2.13 Test and Debug Modules Interface
        14. 4.2.2.14 Flash Supply and Test Pads
        15. 4.2.2.15 Supply for Core Logic: 1.2-V Nominal
        16. 4.2.2.16 Supply for I/O Cells: 3.3-V Nominal
        17. 4.2.2.17 Ground Reference for All Supplies Except VCCAD
    3. 4.3 Pin Multiplexing
      1. 4.3.1 Output Multiplexing
      2. 4.3.2 Multiplexing of Inputs
    4. 4.4 Buffer Type
  5. Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Power-On Hours (POH)
    4. 5.4 Recommended Operating Conditions
    5. 5.5 Input/Output Electrical Characteristics Over Recommended Operating Conditions
    6. 5.6 Power Consumption Over Recommended Operating Conditions
    7. 5.7 Thermal Resistance Characteristics
    8. 5.8 Timing and Switching Characteristics
      1. 5.8.1 SYSCLK (Frequencies)
        1. 5.8.1.1 Switching Characteristics over Recommended Operating Conditions for Clock Domains
        2. 5.8.1.2 Wait States Required - PGE and PZ Packages
  6. System Information and Electrical Specifications
    1. 6.1  Device Power Domains
    2. 6.2  Voltage Monitor Characteristics
      1. 6.2.1 Important Considerations
      2. 6.2.2 Voltage Monitor Operation
      3. 6.2.3 Supply Filtering
    3. 6.3  Power Sequencing and Power-On Reset
      1. 6.3.1 Power-Up Sequence
      2. 6.3.2 Power-Down Sequence
      3. 6.3.3 Power-On Reset: nPORRST
        1. 6.3.3.1 nPORRST Electrical and Timing Requirements
    4. 6.4  Warm Reset (nRST)
      1. 6.4.1 Causes of Warm Reset
      2. 6.4.2 nRST Timing Requirements
    5. 6.5  ARM Cortex-R4F CPU Information
      1. 6.5.1 Summary of ARM Cortex-R4F CPU Features
      2. 6.5.2 ARM Cortex-R4F CPU Features Enabled by Software
      3. 6.5.3 Dual Core Implementation
      4. 6.5.4 Duplicate Clock Tree After GCLK
      5. 6.5.5 ARM Cortex-R4F CPU Compare Module (CCM) for Safety
      6. 6.5.6 CPU Self-Test
        1. 6.5.6.1 Application Sequence for CPU Self-Test
        2. 6.5.6.2 CPU Self-Test Clock Configuration
        3. 6.5.6.3 CPU Self-Test Coverage
    6. 6.6  Clocks
      1. 6.6.1 Clock Sources
        1. 6.6.1.1 Main Oscillator
          1. 6.6.1.1.1 Timing Requirements for Main Oscillator
        2. 6.6.1.2 Low-Power Oscillator
          1. 6.6.1.2.1 Features
          2. 6.6.1.2.2 LPO Electrical and Timing Specifications
        3. 6.6.1.3 Phase-Locked Loop (PLL) Clock Module
          1. 6.6.1.3.1 Block Diagram
          2. 6.6.1.3.2 PLL Timing Specifications
        4. 6.6.1.4 External Clock Inputs
      2. 6.6.2 Clock Domains
        1. 6.6.2.1 Clock Domain Descriptions
        2. 6.6.2.2 Mapping of Clock Domains to Device Modules
      3. 6.6.3 Clock Test Mode
    7. 6.7  Clock Monitoring
      1. 6.7.1 Clock Monitor Timings
      2. 6.7.2 External Clock (ECLK) Output Functionality
      3. 6.7.3 Dual Clock Comparators
        1. 6.7.3.1 Features
        2. 6.7.3.2 Mapping of DCC Clock Source Inputs
    8. 6.8  Glitch Filters
    9. 6.9  Device Memory Map
      1. 6.9.1 Memory Map Diagram
      2. 6.9.2 Memory Map Table
      3. 6.9.3 Special Consideration for CPU Access Errors Resulting in Imprecise Aborts
      4. 6.9.4 Master/Slave Access Privileges
      5. 6.9.5 Special Notes on Accesses to Certain Slaves
    10. 6.10 Flash Memory
      1. 6.10.1 Flash Memory Configuration
      2. 6.10.2 Main Features of Flash Module
      3. 6.10.3 ECC Protection for Flash Accesses
      4. 6.10.4 Flash Access Speeds
      5. 6.10.5 Program Flash
      6. 6.10.6 Data Flash
    11. 6.11 Tightly Coupled RAM Interface Module
      1. 6.11.1 Features
      2. 6.11.2 TCRAMW ECC Support
    12. 6.12 Parity Protection for Accesses to Peripheral RAMs
    13. 6.13 On-Chip SRAM Initialization and Testing
      1. 6.13.1 On-Chip SRAM Self-Test Using PBIST
        1. 6.13.1.1 Features
        2. 6.13.1.2 PBIST RAM Groups
      2. 6.13.2 On-Chip SRAM Auto Initialization
    14. 6.14 Vectored Interrupt Manager
      1. 6.14.1 VIM Features
      2. 6.14.2 Interrupt Request Assignments
    15. 6.15 DMA Controller
      1. 6.15.1 DMA Features
      2. 6.15.2 Default DMA Request Map
    16. 6.16 Real-Time Interrupt Module
      1. 6.16.1 Features
      2. 6.16.2 Block Diagrams
      3. 6.16.3 Clock Source Options
      4. 6.16.4 Network Time Synchronization Inputs
    17. 6.17 Error Signaling Module
      1. 6.17.1 ESM Features
      2. 6.17.2 ESM Channel Assignments
    18. 6.18 Reset/Abort/Error Sources
    19. 6.19 Digital Windowed Watchdog
    20. 6.20 Debug Subsystem
      1. 6.20.1 Block Diagram
      2. 6.20.2 Debug Components Memory Map
      3. 6.20.3 JTAG Identification Code
      4. 6.20.4 Debug ROM
      5. 6.20.5 JTAG Scan Interface Timings
      6. 6.20.6 Advanced JTAG Security Module
      7. 6.20.7 Boundary Scan Chain
  7. Peripheral Information and Electrical Specifications
    1. 7.1  I/O Timings
      1. 7.1.1 Input Timings
      2. 7.1.2 Output Timings
        1. 7.1.2.1 Low-EMI Output Buffers
    2. 7.2  Enhanced PWM Modules (ePWM)
      1. 7.2.1 ePWM Clocking and Reset
      2. 7.2.2 Synchronization of ePWMx Time-Base Counters
      3. 7.2.3 Synchronizing all ePWM Modules to the N2HET1 Module Time Base
      4. 7.2.4 Phase-Locking the Time-Base Clocks of Multiple ePWM Modules
      5. 7.2.5 ePWM Synchronization with External Devices
      6. 7.2.6 ePWM Trip Zones
        1. 7.2.6.1 Trip Zones TZ1n, TZ2n, TZ3n
        2. 7.2.6.2 Trip Zone TZ4n
        3. 7.2.6.3 Trip Zone TZ5n
        4. 7.2.6.4 Trip Zone TZ6n
      7. 7.2.7 Triggering of ADC Start of Conversion Using ePWMx SOCA and SOCB Outputs
      8. 7.2.8 Enhanced Translator-Pulse Width Modulator (ePWMx) Timings
    3. 7.3  Enhanced Capture Modules (eCAP)
      1. 7.3.1 Clock Enable Control for eCAPx Modules
      2. 7.3.2 PWM Output Capability of eCAPx
      3. 7.3.3 Input Connection to eCAPx Modules
      4. 7.3.4 Enhanced Capture Module (eCAP) Electrical Data/Timing
    4. 7.4  Enhanced Quadrature Encoder (eQEP)
      1. 7.4.1 Clock Enable Control for eQEPx Modules
      2. 7.4.2 Using eQEPx Phase Error to Trip ePWMx Outputs
      3. 7.4.3 Input Connections to eQEPx Modules
      4. 7.4.4 Enhanced Quadrature Encoder Pulse (eQEPx) Timing
    5. 7.5  12-Bit Multibuffered Analog-to-Digital Converter (MibADC)
      1. 7.5.1 Features
      2. 7.5.2 Event Trigger Options
        1. 7.5.2.1 MibADC1 Event Trigger Hookup
        2. 7.5.2.2 MibADC2 Event Trigger Hookup
        3. 7.5.2.3 Controlling ADC1 and ADC2 Event Trigger Options Using SOC Output from ePWM Modules
      3. 7.5.3 ADC Electrical and Timing Specifications
      4. 7.5.4 Performance (Accuracy) Specifications
        1. 7.5.4.1 MibADC Nonlinearity Errors
        2. 7.5.4.2 MibADC Total Error
    6. 7.6  General-Purpose Input/Output
      1. 7.6.1 Features
    7. 7.7  Enhanced High-End Timer (N2HET)
      1. 7.7.1 Features
      2. 7.7.2 N2HET RAM Organization
      3. 7.7.3 Input Timing Specifications
      4. 7.7.4 N2HET1 to N2HET2 Synchronization
      5. 7.7.5 N2HET Checking
        1. 7.7.5.1 Internal Monitoring
        2. 7.7.5.2 Output Monitoring Using Dual Clock Comparator (DCC)
      6. 7.7.6 Disabling N2HET Outputs
      7. 7.7.7 High-End Timer Transfer Unit (HET)
        1. 7.7.7.1 Features
        2. 7.7.7.2 Trigger Connections
    8. 7.8  Controller Area Network (DCAN)
      1. 7.8.1 Features
      2. 7.8.2 Electrical and Timing Specifications
    9. 7.9  Local Interconnect Network Interface (LIN)
      1. 7.9.1 LIN Features
    10. 7.10 Serial Communication Interface (SCI)
      1. 7.10.1 Features
    11. 7.11 Inter-Integrated Circuit (I2C) Module
      1. 7.11.1 Features
      2. 7.11.2 I2C I/O Timing Specifications
    12. 7.12 Multibuffered / Standard Serial Peripheral Interface
      1. 7.12.1 Features
      2. 7.12.2 MibSPI Transmit and Receive RAM Organization
      3. 7.12.3 MibSPI Transmit Trigger Events
        1. 7.12.3.1 MibSPI1 Event Trigger Hookup
        2. 7.12.3.2 MibSPI3 Event Trigger Hookup
        3. 7.12.3.3 MibSPI5 Event Trigger Hookup
      4. 7.12.4 MibSPI/SPI Master Mode I/O Timing Specifications
      5. 7.12.5 SPI Slave Mode I/O Timings
  8. Applications, Implementation, and Layout
    1. 8.1 TI Designs or Reference Designs
  9. Device and Documentation Support
    1. 9.1  Getting Started and Next Steps
    2. 9.2  Device and Development-Support Tool Nomenclature
    3. 9.3  Tools and Software
      1. 9.3.1 Kits and Evaluation Modules for Hercules RM MCUs
      2. 9.3.2 Development Tools
      3. 9.3.3 Software
    4. 9.4  Documentation Support
    5. 9.5  Related Links
    6. 9.6  Community Resources
    7. 9.7  Trademarks
    8. 9.8  Electrostatic Discharge Caution
    9. 9.9  Glossary
    10. 9.10 Device Identification
      1. 9.10.1 Device Identification Code Register
      2. 9.10.2 Die Identification Registers
    11. 9.11 Module Certifications
      1. 9.11.1 DCAN Certification
      2. 9.11.2 LIN Certification
        1. 9.11.2.1 LIN Master Mode
        2. 9.11.2.2 LIN Slave Mode - Fixed Baud Rate
        3. 9.11.2.3 LIN Slave Mode - Adaptive Baud Rate
  10. 10Mechanical Packaging and Orderable Information
    1. 10.1 Packaging Information

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • PGE|144
  • PZ|100
散热焊盘机械数据 (封装 | 引脚)
订购信息

System Information and Electrical Specifications

Device Power Domains

The device core logic is split up into multiple power domains to optimize the power for a given application use case. There are five core power domains: PD1, PD2, PD3, PD5, and RAM_PD1. See Section 1.4 for more information.

PD1 is an "always-ON" power domain, which cannot be turned off. Each of the other core power domains can be turned ON/OFF one time during device initialization as per the application requirement. Refer to the Power Management Module (PMM) chapter of the device technical reference manual for more details.

NOTE

The clocks to a module must be turned off before powering down the core domain that contains the module.

Voltage Monitor Characteristics

A voltage monitor is implemented on this device. The purpose of this voltage monitor is to eliminate the requirement for a specific sequence when powering up the core and I/O voltage supplies.

Important Considerations

  • The voltage monitor does not eliminate the need of a voltage supervisor circuit to ensure that the device is held in reset when the voltage supplies are out of range.
  • The voltage monitor only monitors the core supply (VCC) and the I/O supply (VCCIO). The other supplies are not monitored by the VMON. For example, if the VCCAD or VCCP are supplied from a source different from that for VCCIO, then there is no internal voltage monitor for the VCCAD and VCCP supplies.

Voltage Monitor Operation

The voltage monitor generates the Power Good MCU signal (PGMCU) as well as the I/Os Power Good IO signal (PGIO) on the device. During power-up or power-down, the PGMCU and PGIO are driven low when the core or I/O supplies are lower than the specified minimum monitoring thresholds. The PGIO and PGMCU signals being low isolates the core logic as well as the I/O controls during power up or power down of the supplies. This allows the core and I/O supplies to be powered up or down in any order.

When the voltage monitor detects a low voltage on the I/O supply, it will assert a power-on reset. When the voltage monitor detects an out-of-range voltage on the core supply, it asynchronously makes all output pins high impedance, and asserts a power-on reset. The voltage monitor is disabled when the device enters a low power mode.

The VMON also incorporates a glitch filter for the nPORRST input. Refer to Section 6.3.3.1 for the timing information on this glitch filter.

Table 6-1 Voltage Monitoring Specifications

PARAMETER MIN TYP MAX UNIT
VMON Voltage monitoring thresholds VCC low - VCC level below this threshold is detected as too low. 0.75 0.9 1.13 V
VCC high - VCC level above this threshold is detected as too high. 1.40 1.7 2.1
VCCIO low - VCCIO level below this threshold is detected as too low. 1.85 2.4 2.9

Supply Filtering

The VMON has the capability to filter glitches on the VCC and VCCIO supplies.

The following table shows the characteristics of the supply filtering. Glitches in the supply larger than the maximum specification cannot be filtered.

Table 6-2 VMON Supply Glitch Filtering Capability

PARAMETER MIN MAX UNIT
Width of glitch on VCC that can be filtered 250 1000 ns
Width of glitch on VCCIO that can be filtered 250 1000 ns

Power Sequencing and Power-On Reset

Power-Up Sequence

There is no timing dependency between the ramp of the VCCIO and the VCC supply voltage. The power-up sequence starts with the I/O voltage rising above the minimum I/O supply threshold, (see Table 6-4 for more details), core voltage rising above the minimum core supply threshold and the release of power-on reset. The high-frequency oscillator will start up first and its amplitude will grow to an acceptable level. The oscillator start-up time is dependent on the type of oscillator and is provided by the oscillator vendor. The different supplies to the device can be powered up in any order.

The device goes through the following sequential phases during power up.

Table 6-3 Power-Up Phases

Oscillator start-up and validity check 1032 oscillator cycles
eFuse autoload 1160 oscillator cycles
Flash pump power-up 688 oscillator cycles
Flash bank power-up 617 oscillator cycles
Total 3497 oscillator cycles

The CPU reset is released at the end of the above sequence and fetches the first instruction from address 0x00000000.

Power-Down Sequence

The different supplies to the device can be powered down in any order.

Power-On Reset: nPORRST

This is the power-on reset. This reset must be asserted by an external circuitry whenever any power supply is outside the specified recommended range. This signal has a glitch filter on it. It also has an internal pulldown.

nPORRST Electrical and Timing Requirements

Table 6-4 Electrical Requirements for nPORRST

NO. MIN MAX UNIT
VCCPORL VCC low supply level when nPORRST must be active during power up 0.5 V
VCCPORH VCC high supply level when nPORRST must remain active during power up and become active during power down 1.14 V
VCCIOPORL VCCIO / VCCP low supply level when nPORRST must be active during power up 1.1 V
VCCIOPORH VCCIO / VCCP high supply level when nPORRST must remain active during power up and become active during power down 3.0 V
VIL(PORRST) Low-level input voltage of nPORRST VCCIO > 2.5 V 0.2 * VCCIO V
Low-level input voltage of nPORRST VCCIO < 2.5 V 0.5 V
3 tsu(PORRST) Setup time, nPORRST active before VCCIO and VCCP > VCCIOPORL during power up 0 ms
6 th(PORRST) Hold time, nPORRST active after VCC > VCCPORH 1 ms
7 tsu(PORRST) Setup time, nPORRST active before VCC < VCCPORH during power down 2 µs
8 th(PORRST) Hold time, nPORRST active after VCCIO and VCCP > VCCIOPORH 1 ms
9 th(PORRST) Hold time, nPORRST active after VCC < VCCPORL 0 ms
tf(nPORRST)

Filter time nPORRST pin;
pulses less than MIN will be filtered out, pulses greater than MAX will generate a reset.

475 2000 ns
RM44L920 RM44L520 td_nPORRST_spns223.gif
Figure 6-1 shows that there is no timing dependency between the ramp of the VCCIO and the VCC supply voltages.
Figure 6-1 nPORRST Timing Diagram(A)

Warm Reset (nRST)

This is a bidirectional reset signal. The internal circuitry drives the signal low on detecting any device reset condition. An external circuit can assert a device reset by forcing the signal low. On this terminal, the output buffer is implemented as an open drain (drives low only). To ensure an external reset is not arbitrarily generated, TI recommends that an external pullup resistor is connected to this terminal.

This terminal has a glitch filter. It also has an internal pullup

Causes of Warm Reset

Table 6-5 Causes of Warm Reset

DEVICE EVENT SYSTEM STATUS FLAG
Power-Up Reset Exception Status Register, bit 15
Oscillator fail Global Status Register, bit 0
PLL slip Global Status Register, bits 8 and 9
Watchdog exception / Debugger reset Exception Status Register, bit 13
CPU Reset (driven by the CPU STC) Exception Status Register, bit 5
Software Reset Exception Status Register, bit 4
External Reset Exception Status Register, bit 3

nRST Timing Requirements

Table 6-6 nRST Timing Requirements(1)

MIN MAX UNIT
tv(RST) Valid time, nRST active after nPORRST inactive 2256tc(OSC) ns
Valid time, nRST active (all other System reset conditions) 32tc(VCLK)
tf(nRST)

Filter time nRST pin;
pulses less than MIN will be filtered out, pulses greater than MAX will generate a reset

475 2000 ns
Specified values do not include rise/fall times. For rise and fall timings, see Table 7-2.

ARM Cortex-R4F CPU Information

Summary of ARM Cortex-R4F CPU Features

The features of the ARM Cortex-R4F CPU include:

  • An integer unit with integral EmbeddedICE-RT logic.
  • High-speed Advanced Microprocessor Bus Architecture (AMBA) Advanced eXtensible Interfaces (AXI) for Level two (L2) master and slave interfaces.
  • Floating-Point Coprocessor
  • Dynamic branch prediction with a global history buffer, and a 4-entry return stack
  • Low interrupt latency.
  • Nonmaskable interrupt.
  • A Harvard Level one (L1) memory system with:
    • Tightly-Coupled Memory (TCM) interfaces with support for error correction or parity checking memories
    • ARMv7-R architecture Memory Protection Unit (MPU) with 12 regions
  • Dual core logic for fault detection in safety-critical applications.
  • An L2 memory interface:
    • Single 64-bit master AXI interface
    • 64-bit slave AXI interface to TCM RAM blocks
  • A debug interface to a CoreSight Debug Access Port (DAP).
  • Six Hardware Breakpoints
  • Two Watchpoints
  • A Performance Monitoring Unit (PMU).
  • A Vectored Interrupt Controller (VIC) port.

For more information on the ARM Cortex-R4F CPU, see www.arm.com.

ARM Cortex-R4F CPU Features Enabled by Software

The following CPU features are disabled on reset and must be enabled by the application if required.

  • ECC On Tightly-Coupled Memory (TCM) Accesses
  • Hardware Vectored Interrupt (VIC) Port
  • Floating-Point Coprocessor
  • Memory Protection Unit (MPU)

Dual Core Implementation

The device has two Cortex-R4F cores, where the output signals of both CPUs are compared in the CCM-R4 unit. To avoid common mode impacts the signals of the CPUs to be compared are delayed by two clock cycles as shown in Figure 6-2.

RM44L920 RM44L520 dual_core_implementation_pns160.gif Figure 6-2 Dual Core Implementation

The CPUs have a diverse CPU placement given by following requirements:

  • different orientation; for example, CPU1 = "north" orientation, CPU2 = "flip west" orientation
  • dedicated guard ring for each CPU
RM44L920 RM44L520 dual_cpu_orient.gif Figure 6-3 Dual-CPU Orientation

Duplicate Clock Tree After GCLK

The CPU clock domain is split into two clock trees, one for each CPU, with the clock of the second CPU running at the same frequency and in phase to the clock of CPU1. See Figure 6-2.

ARM Cortex-R4F CPU Compare Module (CCM) for Safety

This device has two ARM Cortex-R4F CPU cores, where the output signals of both CPUs are compared in the CCM-R4 unit. To avoid common mode impacts the signals of the CPUs to be compared are delayed in a different way as shown in Figure 6-2.

To avoid an erroneous CCM-R4 compare error, the application software must initialize the registers of both CPUs before the registers are used, including function calls where the register values are pushed onto the stack.

CPU Self-Test

The CPU STC (Self-Test Controller) is used to test the two Cortex-R4F CPU Cores using the Deterministic Logic BIST Controller as the test engine.

The main features of the self-test controller are:

  • Ability to divide the complete test run into independent test intervals
  • Capable of running the complete test as well as running few intervals at a time
  • Ability to continue from the last executed interval (test set) as well as ability to restart from the beginning (First test set)
  • Complete isolation of the self-tested CPU core from rest of the system during the self-test run
  • Ability to capture the Failure interval number
  • Time-out counter for the CPU self-test run as a fail-safe feature

Application Sequence for CPU Self-Test

  1. Configure clock domain frequencies.
  2. Select number of test intervals to be run.
  3. Configure the time-out period for the self-test run.
  4. Enable self-test.
  5. Wait for CPU reset.
  6. In the reset handler, read CPU self-test status to identify any failures.
  7. Retrieve CPU state if required.

For more information see the device Technical Reference Manual.

CPU Self-Test Clock Configuration

The maximum clock rate for the self-test is HCLKmax/2. The STCCLK is divided down from the CPU clock. This divider is configured by the STCCLKDIV register at address 0xFFFFE108.

For more information see the device-specific Technical Reference Manual.

CPU Self-Test Coverage

Table 6-7 lists the CPU self-test coverage achieved for each self-test interval. It also lists the cumulative test cycles. The test time can be calculated by multiplying the number of test cycles with the STC clock period.

Table 6-7 CPU Self-Test Coverage

INTERVALS TEST COVERAGE, % STCCLK CYLCES
0 0 0
1 62.13 1365
2 70.09 2730
3 74.49 4095
4 77.28 5460
5 79.28 6825
6 80.90 8190
7 82.02 9555
8 83.10 10920
9 84.08 12285
10 84.87 13650
11 85.59 15015
12 86.11 16380
13 86.67 17745
14 87.16 19110
15 87.61 20475
16 87.98 21840
17 88.38 23205
18 88.69 24570
19 88.98 25935
20 89.28 27300
21 89.50 28665
22 89.76 30030
23 90.01 31395
24 90.21 32760

Clocks

Clock Sources

Table 6-8 lists the available clock sources on the device. Each clock source can be enabled or disabled using the CSDISx registers in the system module. The clock source number in the table corresponds to the control bit in the CSDISx register for that clock source.

Table 6-8 also shows the default state of each clock source.

Table 6-8 Available Clock Sources

CLOCK
SOURCE NO.
NAME DESCRIPTION DEFAULT STATE
0 OSCIN Main oscillator Enabled
1 PLL1 Output from PLL1 Disabled
2 Reserved Reserved Disabled
3 EXTCLKIN1 External clock input 1 Disabled
4 LFLPO Low-frequency output of internal reference oscillator Enabled
5 HFLPO High-frequency output of internal reference oscillator Enabled
6 Reserved Reserved Disabled
7 EXTCLKIN2 External clock input 2 Disabled

Main Oscillator

The oscillator is enabled by connecting the appropriate fundamental resonator/crystal and load capacitors across the external OSCIN and OSCOUT pins as shown in Figure 6-4. The oscillator is a single-stage inverter held in bias by an integrated bias resistor. This resistor is disabled during leakage test measurement and low power modes.

NOTE

TI strongly encourages each customer to submit samples of the device to the resonator/crystal vendors for validation. The vendors are equipped to determine which load capacitors will best tune their resonator/crystal to the microcontroller device for optimum start-up and operation over temperature and voltage extremes.

An external oscillator source can be used by connecting a 3.3-V clock signal to the OSCIN pin and leaving the OSCOUT pin unconnected (open) as shown in Figure 6-4.

RM44L920 RM44L520 clock_connection_pns160.gif Figure 6-4 Recommended Crystal/Clock Connection

Timing Requirements for Main Oscillator

Table 6-9 Timing Requirements for Main Oscillator

MIN NOM MAX UNIT
tc(OSC) Cycle time, OSCIN (when using a sine-wave input) 50 200 ns
tw(OSCIL) Pulse duration, OSCIN low (when input to the OSCIN is a square wave) 15 ns
tw(OSCIH) Pulse duration, OSCIN high (when input to the OSCIN is a square wave) 15 ns

Low-Power Oscillator

The Low-Power Oscillator (LPO) is comprised of two oscillators — HF LPO and LF LPO, in a single macro.

Features

The main features of the LPO are:

  • Supplies a clock at extremely low power for power-saving modes. This is connected as clock source 4 of the Global Clock Module (GCM).
  • Supplies a high-frequency clock for non-timing-critical systems. This is connected as clock source 5 of the GCM.
  • Provides a comparison clock for the crystal oscillator failure detection circuit.

RM44L920 RM44L520 LPO_Block_Diagram_spns225.gif Figure 6-5 LPO Block Diagram

Figure 6-5 shows a block diagram of the internal reference oscillator. This is a low-power oscillator (LPO) and provides two clock sources: one nominally 80 kHz and one nominally 10 MHz.

LPO Electrical and Timing Specifications

Table 6-10 LPO Specifications

PARAMETER MIN TYP MAX UNIT
Clock detection Oscillator fail frequency - lower threshold, using untrimmed LPO output 1.375 2.4 4.875 MHz
Oscillator fail frequency - higher threshold, using untrimmed LPO output 22 38.4 78 MHz
LPO - HF oscillator Untrimmed frequency 5.5 9 19.5 MHz
Trimmed frequency 8 9.6 11 MHz
Start-up time from STANDBY (LPO BIAS_EN high for at least 900 µs) 10 µs
Cold start-up time 900 µs
LPO - LF oscillator Untrimmed frequency 36 85 180 kHz
Start-up time from STANDBY (LPO BIAS_EN high for at least 900 µs) 100 µs
Cold start-up time 2000 µs

Phase-Locked Loop (PLL) Clock Module

The PLL is used to multiply the input frequency to some higher frequency.

The main features of the PLL are:

  • Frequency modulation can be optionally superimposed on the synthesized frequency of PLL1.
  • Configurable frequency multipliers and dividers
  • Built-in PLL Slip monitoring circuit
  • Option to reset the device on a PLL slip detection

Block Diagram

Figure 6-6 shows a high-level block diagram of the PLL macro on this microcontroller.

RM44L920 RM44L520 FMzPLLx_block_diagram_1oscin_pns160.gif Figure 6-6 PLL Block Diagram

PLL Timing Specifications

Table 6-11 PLL Timing Specifications

PARAMETER MIN MAX UNIT
fINTCLK PLL1 Reference Clock frequency 1 20 MHz
fpost_ODCLK Post-ODCLK – PLL1 Post-divider input clock frequency 400 MHz
fVCOCLK VCOCLK – PLL1 Output Divider (OD) input clock frequency 150 550 MHz

External Clock Inputs

The device supports up to two external clock inputs. This clock input must be a square-wave input. Table 6-12 specifies the electrical and timing requirements for these clock inputs. The external clock sources are not checked for validity. They are assumed valid when enabled.

Table 6-12 External Clock Timing and Electrical Specifications

PARAMETER MIN MAX UNIT
fEXTCLKx External clock input frequency 80 MHz
tw(EXTCLKIN)H EXTCLK high-pulse duration 6 ns
tw(EXTCLKIN)L EXTCLK low-pulse duration 6 ns
viL(EXTCLKIN) Low-level input voltage –0.3 0.8 V
viH(EXTCLKIN) High-level input voltage 2 VCCIO + 0.3 V

Clock Domains

Clock Domain Descriptions

Table 6-13 lists the device clock domains and their default clock sources. The table also shows the system module control register that is used to select an available clock source for each clock domain.

Table 6-13 Clock Domain Descriptions

CLOCK DOMAIN DEFAULT
SOURCE
SOURCE SELECTION
REGISTER
SPECIAL CONSIDERATIONS
HCLK OSCIN GHVSRC
  • Is disabled through the CDDISx registers bit 1
  • Used for all system modules including DMA, ESM
GCLK OSCIN GHVSRC
  • Always the same frequency as HCLK
  • In phase with HCLK
  • Is disabled separately from HCLK through the CDDISx registers bit 0
  • Can be divided by 1 up to 8 when running CPU self-test (LBIST) using the CLKDIV field of the STCCLKDIV register at address 0xFFFFE108
GCLK2 OSCIN GHVSRC
  • Always the same frequency as GCLK
  • 2 cycles delayed from GCLK
  • Is disabled along with GCLK
  • Gets divided by the same divider setting as that for GCLK when running CPU self-test (LBIST)
VCLK OSCIN GHVSRC
  • Divided down from HCLK
  • Can be HCLK/1, HCLK/2, ... or HCLK/16
  • Is disabled separately from HCLK through the CDDISx registers bit 2
VCLK2 OSCIN GHVSRC
  • Divided down from HCLK
  • Can be HCLK/1, HCLK/2, ... or HCLK/16
  • Frequency must be an integer multiple of VCLK frequency
  • Is disabled separately from HCLK through the CDDISx registers bit 3
VCLK4 OSCIN GHVSRC
  • Divided down from HCLK
  • Can be HCLK/1, HCLK/2, ... or HCLK/16
  • Is disabled separately from HCLK through the CDDISx registers bit 9
VCLKA1 VCLK VCLKASRC
  • Defaults to VCLK as the source
  • Is disabled through the CDDISx registers bit 4
RTICLK VCLK RCLKSRC
  • Defaults to VCLK as the source
  • If a clock source other than VCLK is selected for RTICLK, then the RTICLK frequency must be less than or equal to VCLK/3
    • Application can ensure this by programming the RTI1DIV field of the RCLKSRC register, if necessary
  • Is disabled through the CDDISx registers bit 6

Mapping of Clock Domains to Device Modules

Each clock domain has a dedicated functionality as shown in Figure 6-7 .

RM44L920 RM44L520 dev_clock_domains_Archer_spns225.gif Figure 6-7 Device Clock Domains

Clock Test Mode

The RM4x platform architecture defines a special mode that allows various clock signals to be selected and output on the ECLK pin and N2HET1[12] device outputs. This special mode, Clock Test Mode, is very useful for debugging purposes and can be configured through the CLKTEST register in the system module. See Table 6-14 for the CLKTEST bits value and signal selection.

Table 6-14 Clock Test Mode Options

SEL_ECP_PIN
=
CLKTEST[4-0]
SIGNAL ON ECLK SEL_GIO_PIN
=
CLKTEST[11-8]
SIGNAL ON N2HET1[12]
00000 Oscillator 0000 Oscillator Valid Status
00001 Main PLL free-running clock output 0001 Main PLL Valid status
00010 Reserved 0010 Reserved
00011 EXTCLKIN1 0011 Reserved
00100 LFLPO 0100 Reserved
00101 HFLPO 0101 HFLPO Valid status
00110 Reserved 0110 Reserved
00111 EXTCLKIN2 0111 Reserved
01000 GCLK 1000 LFLPO
01001 RTI Base 1001 Oscillator Valid status
01010 Reserved 1010 Oscillator Valid status
01011 VCLKA1 1011 Oscillator Valid status
01100 Reserved 1100 Oscillator Valid status
01101 Reserved 1101 Reserved
01110 Reserved 1110 Reserved
01111 Reserved 1111 Oscillator Valid status
10000 Reserved
10001 HCLK
10010 VCLK
10011 VCLK2
10100 Reserved
10101 VCLK4
10110 Reserved
10111 Reserved
11000 Reserved
Others Reserved

Clock Monitoring

The LPO Clock Detect (LPOCLKDET) module consists of a clock monitor (CLKDET) and an internal LPO.

The LPO provides two different clock sources – a low frequency (LFLPO) and a high frequency (HFLPO).

The CLKDET is a supervisor circuit for an externally supplied clock signal (OSCIN). In case the OSCIN frequency falls out of a frequency window, the CLKDET flags this condition in the global status register (GLBSTAT bit 0: OSC FAIL) and switches all clock domains sourced by OSCIN to the HFLPO clock (limp mode clock).

The valid OSCIN frequency range is defined as: fHFLPO / 4 < fOSCIN < fHFLPO * 4.

Clock Monitor Timings

For more information on LPO and Clock detection, see Table 6-10.

RM44L920 RM44L520 LPO_Clk_Detection_pns160.gif Figure 6-8 LPO and Clock Detection, Untrimmed HFLPO

External Clock (ECLK) Output Functionality

The ECLK pin can be configured to output a prescaled clock signal indicative of an internal device clock. This output can be externally monitored as a safety diagnostic.

Dual Clock Comparators

The Dual Clock Comparator (DCC) module determines the accuracy of selectable clock sources by counting the pulses of two independent clock sources (counter 0 and counter 1). If one clock is out of spec, an error signal is generated. For example, the DCC1 can be configured to use HFLPO as the reference clock (for counter 0) and VCLK as the "clock under test" (for counter 1). This configuration allows the DCC1 to monitor the PLL output clock when VCLK is using the PLL output as its source.

An additional use of this module is to measure the frequency of a selectable clock source, using the input clock as a reference, by counting the pulses of two independent clock sources. Counter 0 generates a fixed-width counting window after a preprogrammed number of pulses. Counter 1 generates a fixed-width pulse (1 cycle) after a preprogrammed number of pulses. This pulse sets as an error signal if counter 1 does not reach 0 within the counting window generated by counter 0.

Features

  • Takes two different clock sources as input to two independent counter blocks.
  • One of the clock sources is the known-good, or reference clock; the second clock source is the "clock under test."
  • Each counter block is programmable with initial, or seed values.
  • The counter blocks start counting down from their seed values at the same time; a mismatch from the expected frequency for the clock under test generates an error signal which is used to interrupt the CPU.

Mapping of DCC Clock Source Inputs

Table 6-15 DCC1 Counter 0 Clock Sources

CLOCK SOURCE[3:0] CLOCK NAME
Others Oscillator (OSCIN)
0x5 High-frequency LPO
0xA Test clock (TCK)

Table 6-16 DCC1 Counter 1 Clock Sources

KEY[3:0] CLOCK SOURCE[3:0] CLOCK NAME
Others N2HET1[31]
0x0 Main PLL free-running clock output
0x1 Reserved
0x2 Low-frequency LPO
0xA 0x3 High-frequency LPO
0x4 Reserved
0x5 EXTCLKIN1
0x6 EXTCLKIN2
0x7 Reserved
0x8 - 0xF VCLK

Table 6-17 DCC2 Counter 0 Clock Sources

CLOCK SOURCE [3:0] CLOCK NAME
Others Oscillator (OSCIN)
0xA Test clock (TCK)

Table 6-18 DCC2 Counter 1 Clock Sources

KEY [3:0] CLOCK SOURCE [3:0] CLOCK NAME
Others N2HET2[0]
0xA 00x0 - 0x7 Reserved
0x8 - 0xF VCLK

Glitch Filters

A glitch filter is present on the following signals.

Table 6-19 Glitch Filter Timing Specifications

PIN PARAMETER MIN MAX UNIT
nPORRST tf(nPORRST)

Filter time nPORRST pin; pulses less than MIN will be filtered out, pulses greater than MAX will generate a reset(1)

475 2000 ns
nRST tf(nRST)

Filter time nRST pin; pulses less than MIN will be filtered out, pulses greater than MAX will generate a reset

475 2000 ns
TEST tf(TEST)

Filter time TEST pin; pulses less than MIN will be filtered out, pulses greater than MAX will pass through

475 2000 ns
The glitch filter design on the nPORRST signal is designed such that no size pulse will reset any part of the microcontroller (flash pump, I/O pins, and so forth) without also generating a valid reset signal to the CPU.

Device Memory Map

Memory Map Diagram

Figure 6-9 shows the device memory map.

RM44L920 RM44L520 memory_map_f17_spns225.gif Figure 6-9 Memory Map

The Flash memory is mirrored to support ECC logic testing. The base address of the mirrored Flash image is 0x2000 0000.

Memory Map Table

See Figure 1-1 for block diagrams showing the devices interconnect.

Table 6-20 Device Memory Map

MODULE NAME FRAME CHIP SELECT FRAME ADDRESS RANGE FRAME SIZE ACTUAL SIZE RESPONSE FOR ACCESS TO UNIMPLEMENTED LOCATIONS IN FRAME
START END
Memories tightly coupled to the ARM Cortex-R4F CPU
TCM Flash CS0 0x0000_0000 0x00FF_FFFF 16MB 1MB Abort
TCM RAM + RAM ECC CSRAM0 0x0800_0000 0x0BFF_FFFF 64MB 128KB
Mirrored Flash Flash mirror frame 0x2000_0000 0x20FF_FFFF 16MB 1MB
Flash Module Bus2 Interface
Customer OTP, TCM Flash Banks 0xF000_0000 0xF000_1FFF 8KB 4KB Abort
Customer OTP,
Bank 7
0xF000_E000 0xF000_FFFF 8KB 1KB
Customer OTP–ECC, TCM Flash Banks 0xF004_0000 0xF004_03FF 1KB 512B
Customer OTP–ECC,
Bank 7
0xF004_1C00 0xF004_1FFF 1KB 128B
TI OTP, TCM Flash Banks 0xF008_0000 0xF008_1FFF 8KB 4KB
TI OTP,
Bank 7
0xF008_E000 0xF008_FFFF 8KB 1KB
TI OTP–ECC, TCM Flash Banks 0xF00C_0000 0xF00C_03FF 1KB 512B
TI OTP–ECC,
Bank 7
0xF00C_1C00 0xF00C_1FFF 1KB 128B
Bank 7 – ECC 0xF010_0000 0xF013_FFFF 256KB 8KB
Bank 7 0xF020_0000 0xF03F_FFFF 2MB 64KB
Flash Data Space ECC 0xF040_0000 0xF04F_FFFF 1MB 128KB
SCR5: Enhanced Timer Peripherals
ePWM1 0xFCF7_8C00 0xFCF7_8CFF 256B 256B Abort
ePWM2 0xFCF7_8D00 0xFCF7_8DFF 256B 256B Abort
ePWM3 0xFCF7_8E00 0xFCF7_8EFF 256B 256B Abort
ePWM4 0xFCF7_8F00 0xFCF7_8FFF 256B 256B Abort
ePWM5 0xFCF7_9000 0xFCF7_90FF 256B 256B Abort
ePWM6 0xFCF7_9100 0xFCF7_91FF 256B 256B Abort
ePWM7 0xFCF7_9200 0xFCF7_92FF 256B 256B Abort
eCAP1 0xFCF7_9300 0xFCF7_93FF 256B 256B Abort
eCAP2 0xFCF7_9400 0xFCF7_94FF 256B 256B Abort
eCAP3 0xFCF7_9500 0xFCF7_95FF 256B 256B Abort
eCAP4 0xFCF7_9600 0xFCF7_96FF 256B 256B Abort
eCAP5 0xFCF7_9700 0xFCF7_97FF 256B 256B Abort
eCAP6 0xFCF7_9800 0xFCF7_98FF 256B 256B Abort
eQEP1 0xFCF7_9900 0xFCF7_99FF 256B 256B Abort
eQEP2 0xFCF7_9A00 0xFCF7_9AFF 256B 256B Abort
Cyclic Redundancy Checker (CRC) Module Registers
CRC CRC frame 0xFE00_0000 0xFEFF_FFFF 16MB 512B Accesses above 0x200 generate abort.
Peripheral Memories
MIBSPI5 RAM PCS[5] 0xFF0A_0000 0xFF0B_FFFF 128KB 2KB Abort for accesses above 2KB
MIBSPI3 RAM PCS[6] 0xFF0C_0000 0xFF0D_FFFF 128KB 2KB Abort for accesses above 2KB
MIBSPI1 RAM PCS[7] 0xFF0E_0000 0xFF0F_FFFF 128KB 2KB Abort for accesses above 2KB
DCAN3 RAM PCS[13] 0xFF1A_0000 0xFF1B_FFFF 128KB 2KB Wrap around for accesses to unimplemented address offsets lower than 0x7FF. Abort generated for accesses beyond offset 0x800.
DCAN2 RAM PCS[14] 0xFF1C_0000 0xFF1D_FFFF 128KB 2KB Wrap around for accesses to unimplemented address offsets lower than 0x7FF. Abort generated for accesses beyond offset 0x800.
DCAN1 RAM PCS[15] 0xFF1E_0000 0xFF1F_FFFF 128KB 2KB Wrap around for accesses to unimplemented address offsets lower than 0x7FF. Abort generated for accesses beyond offset 0x800.
MIBADC2 RAM PCS[29] 0xFF3A_0000 0xFF3B_FFFF 128KB 8KB Wrap around for accesses to unimplemented address offsets lower than 0x1FFF. Abort generated for accesses beyond 0x1FFF.
MIBADC2
Look-Up Table
384B Look-Up Table for ADC2 wrapper. Starts at address offset 0x2000 and ends at address offset 0x217F. Wrap around for accesses between offsets 0x0180 and 0x3FFF. Abort generated for accesses beyond offset 0x4000.
MIBADC1 RAM PCS[31] 0xFF3E_0000 0xFF3F_FFFF 128KB 8KB Wrap around for accesses to unimplemented address offsets lower than 0x1FFF. Abort generated for accesses beyond 0x1FFF.
MibADC1
Look-Up Table
384B Look-Up Table for ADC1 wrapper. Starts at address offset 0x2000 and ends at address offset 0x217F. Wrap around for accesses between offsets 0x0180 and 0x3FFF. Abort generated for accesses beyond offset 0x4000.
N2HET2 RAM PCS[34] 0xFF44_0000 0xFF45_FFFF 128KB 16KB Wrap around for accesses to unimplemented address offsets lower than 0x3FFF. Abort generated for accesses beyond 0x3FFF.
N2HET1 RAM PCS[35] 0xFF46_0000 0xFF47_FFFF 128KB 16KB Wrap around for accesses to unimplemented address offsets lower than 0x3FFF. Abort generated for accesses beyond 0x3FFF.
N2HET2 TU2 RAM PCS[38] 0xFF4C_0000 0xFF4D_FFFF 128KB 1KB Abort
N2HET1 TU1 RAM PCS[39] 0xFF4E_0000 0xFF4F_FFFF 128KB 1KB Abort
Debug Components
CoreSight Debug ROM CSCS0 0xFFA0_0000 0xFFA0_0FFF 4KB 4KB Reads return zeros, writes have no effect
Cortex-R4F Debug CSCS1 0xFFA0_1000 0xFFA0_1FFF 4KB 4KB Reads return zeros, writes have no effect
Peripheral Control Registers
HTU1 PS[22] 0xFFF7_A400 0xFFF7_A4FF 256B 256B Reads return zeros, writes have no effect
HTU2 PS[22] 0xFFF7_A500 0xFFF7_A5FF 256B 256B Reads return zeros, writes have no effect
N2HET1 PS[17] 0xFFF7_B800 0xFFF7_B8FF 256B 256B Reads return zeros, writes have no effect
N2HET2 PS[17] 0xFFF7_B900 0xFFF7_B9FF 256B 256B Reads return zeros, writes have no effect
GIO PS[16] 0xFFF7_BC00 0xFFF7_BDFF 512B 256B Reads return zeros, writes have no effect
MIBADC1 PS[15] 0xFFF7_C000 0xFFF7_C1FF 512B 512B Reads return zeros, writes have no effect
MIBADC2 PS[15] 0xFFF7_C200 0xFFF7_C3FF 512B 512B Reads return zeros, writes have no effect
I2C PS[10] 0xFFF7_D400 0xFFF7_D4FF 256B 256B Reads return zeros, writes have no effect
DCAN1 PS[8] 0xFFF7_DC00 0xFFF7_DDFF 512B 512B Reads return zeros, writes have no effect
DCAN2 PS[8] 0xFFF7_DE00 0xFFF7_DFFF 512B 512B Reads return zeros, writes have no effect
DCAN3 PS[7] 0xFFF7_E000 0xFFF7_E1FF 512B 512B Reads return zeros, writes have no effect
LIN PS[6] 0xFFF7_E400 0xFFF7_E4FF 256B 256B Reads return zeros, writes have no effect
SCI PS[6] 0xFFF7_E500 0xFFF7_E5FF 256B 256B Reads return zeros, writes have no effect
MibSPI1 PS[2] 0xFFF7_F400 0xFFF7_F5FF 512B 512B Reads return zeros, writes have no effect
SPI2 PS[2] 0xFFF7_F600 0xFFF7_F7FF 512B 512B Reads return zeros, writes have no effect
MibSPI3 PS[1] 0xFFF7_F800 0xFFF7_F9FF 512B 512B Reads return zeros, writes have no effect
SPI4 PS[1] 0xFFF7_FA00 0xFFF7_FBFF 512B 512B Reads return zeros, writes have no effect
MibSPI5 PS[0] 0xFFF7_FC00 0xFFF7_FDFF 512B 512B Reads return zeros, writes have no effect
System Modules Control Registers and Memories
DMA RAM PPCS0 0xFFF8_0000 0xFFF8_0FFF 4KB 4KB Abort
VIM RAM PPCS2 0xFFF8_2000 0xFFF8_2FFF 4KB 1KB Wrap around for accesses to unimplemented address offsets between 1KB and 4KB.
Flash Module PPCS7 0xFFF8_7000 0xFFF8_7FFF 4KB 4KB Abort
eFuse Controller PPCS12 0xFFF8_C000 0xFFF8_CFFF 4KB 4KB Abort
Power Management Module (PMM) PPSE0 0xFFFF_0000 0xFFFF_01FF 512B 512B Abort
PCR registers PPS0 0xFFFF_E000 0xFFFF_E0FF 256B 256B Reads return zeros, writes have no effect
System Module - Frame 2
(see device TRM)
PPS0 0xFFFF_E100 0xFFFF_E1FF 256B 256B Reads return zeros, writes have no effect
PBIST PPS1 0xFFFF_E400 0xFFFF_E5FF 512B 512B Reads return zeros, writes have no effect
STC PPS1 0xFFFF_E600 0xFFFF_E6FF 256B 256B Generates address error interrupt, if enabled
IOMM Multiplexing Control Module PPS2 0xFFFF_EA00 0xFFFF_EBFF 512B 512B Reads return zeros, writes have no effect
DCC1 PPS3 0xFFFF_EC00 0xFFFF_ECFF 256B 256B Reads return zeros, writes have no effect
DMA PPS4 0xFFFF_F000 0xFFFF_F3FF 1KB 1KB Reads return zeros, writes have no effect
DCC2 PPS5 0xFFFF_F400 0xFFFF_F4FF 256B 256B Reads return zeros, writes have no effect
ESM PPS5 0xFFFF_F500 0xFFFF_F5FF 256B 256B Reads return zeros, writes have no effect
CCMR4 PPS5 0xFFFF_F600 0xFFFF_F6FF 256B 256B Reads return zeros, writes have no effect
RAM ECC even PPS6 0xFFFF_F800 0xFFFF_F8FF 256B 256B Reads return zeros, writes have no effect
RAM ECC odd PPS6 0xFFFF_F900 0xFFFF_F9FF 256B 256B Reads return zeros, writes have no effect
RTI + DWWD PPS7 0xFFFF_FC00 0xFFFF_FCFF 256B 256B Reads return zeros, writes have no effect
VIM Parity PPS7 0xFFFF_FD00 0xFFFF_FDFF 256B 256B Reads return zeros, writes have no effect
VIM PPS7 0xFFFF_FE00 0xFFFF_FEFF 256B 256B Reads return zeros, writes have no effect
System Module - Frame 1
(see device TRM)
PPS7 0xFFFF_FF00 0xFFFF_FFFF 256B 256B Reads return zeros, writes have no effect

Special Consideration for CPU Access Errors Resulting in Imprecise Aborts

Any CPU write access to a Normal or Device type memory, which generates a fault, will generate an imprecise abort. The imprecise abort exception is disabled by default and must be enabled for the CPU to handle this exception. The imprecise abort handling is enabled by clearing the "A" bit in the CPU program status register (CPSR).

Master/Slave Access Privileges

Table 6-21 lists the access permissions for each bus master on the device. A bus master is a module that can initiate a read or a write transaction on the device.

Each slave module on the main interconnect is listed in the table. Yes indicates that the module listed in the MASTERS column can access that slave module.

Table 6-21 Master / Slave Access Matrix

MASTERS ACCESS MODE SLAVES ON MAIN SCR
Flash Module Bus2 Interface:
OTP, ECC, Bank 7
Non-CPU Accesses to Program Flash and CPU Data RAM CRC Slave Interfaces Peripheral Control Registers, All Peripheral Memories, And All System Module Control Registers And Memories
CPU READ User/Privilege Yes Yes Yes Yes Yes
CPU WRITE User/Privilege No Yes Yes Yes Yes
DMA User Yes Yes Yes Yes Yes
DAP Privilege Yes Yes Yes Yes Yes
HTU1 Privilege No Yes Yes Yes Yes
HTU2 Privilege No Yes Yes Yes Yes

Special Notes on Accesses to Certain Slaves

Write accesses to the Power Domain Management Module (PMM) control registers are limited to the CPU (master id = 1). The other masters can only read from these registers.

A debugger can also write to the PMM registers. The master-id check is disabled in debug mode.

The device contains dedicated logic to generate a bus error response on any access to a module that is in a power domain that has been turned off.

Flash Memory

Flash Memory Configuration

Flash Bank: A separate block of logic consisting of 1 to 16 sectors. Each flash bank normally has a customer-OTP and a TI-OTP area. These flash sectors share input/output buffers, data paths, sense amplifiers, and control logic.

Flash Sector: A contiguous region of flash memory which must be erased simultaneously due to physical construction constraints.

Flash Pump: A charge pump which generates all the voltages required for reading, programming, or erasing the flash banks.

Flash Module: Interface circuitry required between the host CPU and the flash banks and pump module.

Table 6-22 Flash Memory Banks and Sectors

MEMORY ARRAYS (OR BANKS) SECTOR NO. SEGMENT LOW ADDRESS HIGH ADDRESS
BANK0 (1MB)(1) 0 16KB 0x0000_0000 0x0000_3FFF
1 16KB 0x0000_4000 0x0000_7FFF
2 16KB 0x0000_8000 0x0000_BFFF
3 16KB 0x0000_C000 0x0000_FFFF
4 16KB 0x0001_0000 0x0001_3FFF
5 16KB 0x0001_4000 0x0001_7FFF
6 32KB 0x0001_8000 0x0001_FFFF
7 128KB 0x0002_0000 0x0003_FFFF
8 128KB 0x0004_0000 0x0005_FFFF
9 128KB 0x0006_0000 0x0007_FFFF
10 128KB 0x0008_0000 0x0009_FFFF
11 128KB 0x000A_0000 0x000B_FFFF
12(5) 128KB 0x000C_0000 0x000D_FFFF
13(5) 128KB 0x000E_0000 0x000F_FFFF
BANK7 (64KB) for EEPROM emulation(2)(3)(4) 0 4KB 0xF020_0000 0xF020_0FFF
1 4KB 0xF020_1000 0xF020_1FFF
2 4KB 0xF020_2000 0xF020_2FFF
3 4KB 0xF020_3000 0xF020_3FFF
4 4KB 0xF020_4000 0xF020_4FFF
5 4KB 0xF020_5000 0xF020_5FFF
6 4KB 0xF020_6000 0xF020_6FFF
7 4KB 0xF020_7000 0xF020_7FFF
8 4KB 0xF020_8000 0xF020_8FFF
9 4KB 0xF020_9000 0xF020_9FFF
10 4KB 0xF020_A000 0xF020_AFFF
11 4KB 0xF020_B000 0xF020_BFFF
12 4KB 0xF020_C000 0xF020_CFFF
13 4KB 0xF020_D000 0xF020_DFFF
14 4KB 0xF020_E000 0xF020_EFFF
15 4KB 0xF020_F000 0xF020_FFFF
Flash bank0 is a 144-bit-wide bank with ECC support.
Flash bank7 is a 72-bit-wide bank with ECC support.
The flash bank7 can be programmed while executing code from flash bank0.
Code execution is not allowed from flash bank7.
Sectors 12 and 13 are not accessible or included in the RM44L520 configuration.

Main Features of Flash Module

  • Support for multiple flash banks for program and/or data storage
  • Simultaneous read access on a bank while performing program or erase operation on any other bank
  • Integrated state machines to automate flash erase and program operations
  • Pipelined mode operation to improve instruction access interface bandwidth
  • Support for Single Error Correction Double Error Detection (SECDED) block inside Cortex-R4F CPU
    • Error address is captured for host system debugging
  • Support for a rich set of diagnostic features

ECC Protection for Flash Accesses

All accesses to the program flash memory are protected by SECDED logic embedded inside the CPU. The flash module provides 8 bits of ECC code for 64 bits of instructions or data fetched from the flash memory. The CPU calculates the expected ECC code based on the 64 bits received and compares it with the ECC code returned by the flash module. A single-bit error is corrected and flagged by the CPU, while a multibit error is only flagged. The CPU signals an ECC error through its Event bus. This signaling mechanism is not enabled by default and must be enabled by setting the "X" bit of the Performance Monitor Control Register, c9.

MRC p15,#0,r1,c9,c12,#0 ;Enabling Event monitor states ORR r1, r1, #0x00000010 MCR p15,#0,r1,c9,c12,#0 ;Set 4th bit (‘X’) of PMNC register MRC p15,#0,r1,c9,c12,#0

The application must also explicitly enable the ECC checking of the CPU for accesses on the CPU ATCM and BTCM interfaces. These are connected to the program flash and data RAM, respectively. ECC checking for these interfaces can be done by setting the B1TCMPCEN, B0TCMPCEN, and ATCMPCEN bits of the System Control Coprocessor Auxiliary Control Register, c1.

MRC p15, #0, r1, c1, c0, #1 ORR r1, r1, #0x0e000000 ;Enable ECC checking for ATCM and BTCMs DMB MCR p15, #0, r1, c1, c0, #1

Flash Access Speeds

For information on flash memory access speeds and the relevant wait states required, see Section 5.8.1.2.

Program Flash

Table 6-23 Timing Requirements for Program Flash

MIN NOM MAX UNIT
tprog(144bit) Wide Word (144-bit) programming time 40 300 µs
tprog(Total) 1MByte programming time(1) –40°C to 105°C 11 s
0°C to 60°C, for first 25 cycles 2.8 5.5 s
tprog(Total) 768KB programming time(1) –40°C to 105°C 8 s
0°C to 60°C, for first 25 cycles 2 4 s
terase(bank0) Sector/Bank erase time(2) –40°C to 105°C 0.03 4 s
0°C to 60°C, for first 25 cycles 16 100 ms
twec Write/erase cycles with 15-year Data Retention requirement –40°C to 105°C 1000 cycles
This programming time includes overhead of state machine, but does not include data transfer time. The programming time assumes programming 144 bits at a time at the maximum specified operating frequency.
During bank erase, the selected sectors are erased simultaneously. The time to erase the bank is specified as equal to the time to erase a sector.

Data Flash

Table 6-24 Timing Requirements for Data Flash

MIN NOM MAX UNIT
tprog(144bit) Wide Word (72-bit) programming time 47 310 µs
tprog(Total) EEPROM Emulation (bank 7) 64KByte programming time(1) –40°C to 105°C 2.6 s
0°C to 60°C, for first 25 cycles 775 1435 ms
terase(bank7) Sector/Bank erase time, EEPROM Emulation (bank 7) –40°C to 105°C 0.2 8 s
0°C to 60°C, for first 25 cycles 14 100 ms
twec Write/erase cycles with 15-year Data Retention requirement –40°C to 105°C 100000 cycles
This programming time includes overhead of state machine, but does not include data transfer time. The programming time assumes programming 72 bits at a time at the maximum specified operating frequency.

Tightly Coupled RAM Interface Module

Figure 6-10 shows the connection of the Tightly Coupled RAM (TCRAM) to the Cortex-R4F™ CPU.

RM44L920 RM44L520 tcram_fbd_spns225.gif Figure 6-10 TCRAM Block Diagram

Features

The features of the Tightly Coupled RAM (TCRAM) Module are:

  • Acts as slave to the BTCM interface of the Cortex-R4F CPU
  • Supports CPU internal ECC scheme by providing 64-bit data and 8-bit ECC code
  • Monitors CPU Event Bus and generates single-bit or multibit error interrupts
  • Stores addresses for single-bit and multibit errors
  • Supports RAM trace module
  • Provides CPU address bus integrity checking by supporting parity checking on the address bus
  • Performs redundant address decoding for the RAM bank chip select and ECC select generation logic
  • Provides enhanced safety for the RAM addressing by implementing two 36-bit-wide byte-interleaved RAM banks and generating independent RAM access control signals to the two banks
  • Supports auto-initialization of the RAM banks along with the ECC bits

TCRAMW ECC Support

The TCRAMW passes on the ECC code for each data read by the Cortex-R4F CPU from the RAM. The TCRAMW also stores the ECC port contents of the CPU in the ECC RAM when the CPU does a write to the RAM. The TCRAMW monitors the CPU event bus and provides registers for indicating single-bit or multibit errors and also for identifying the address that caused the single or multi-bit error. The event signaling and the ECC checking for the RAM accesses must be enabled inside the CPU.

For more information, see the device-specific Technical Reference Manual.

Parity Protection for Accesses to Peripheral RAMs

Accesses to some peripheral RAMs are protected by odd/even parity checking. During a read access the parity is calculated based on the data read from the peripheral RAM and compared with the good parity value stored in the parity RAM for that peripheral. If any word fails the parity check, the module generates a parity error signal that is mapped to the Error Signaling Module. The module also captures the peripheral RAM address that caused the parity error.

The parity protection for peripheral RAMs is not enabled by default and must be enabled by the application. Each individual peripheral contains control registers to enable the parity protection for accesses to its RAM.

NOTE

The CPU read access gets the actual data from the peripheral. The application can choose to generate an interrupt whenever a peripheral RAM parity error is detected.

On-Chip SRAM Initialization and Testing

On-Chip SRAM Self-Test Using PBIST

Features

  • Extensive instruction set to support various memory test algorithms
  • ROM-based algorithms allow application to run TI production-level memory tests
  • Independent testing of all on-chip SRAM

PBIST RAM Groups

Table 6-25 PBIST RAM Grouping

MEMORY RAM
GROUP
TEST CLOCK MEM
TYPE
Test Pattern (Algorithm)
TRIPLE READ
SLOW READ
TRIPLE READ
FAST READ
MARCH 13N(1)
TWO PORT
(cycles)
MARCH 13N(1)
SINGLE PORT
(cycles)
ALGO MASK 0x1 ALGO MASK 0x2 ALGO MASK 0x4 ALGO MASK 0x8
PBIST_ROM 1 ROM CLK ROM 24578 8194
STC_ROM 2 ROM CLK ROM 19586 6530
DCAN1 3 VCLK Dual port 25200
DCAN2 4 VCLK Dual port 25200
DCAN3 5 VCLK Dual port 25200
ESRAM1(2) 6 HCLK Single port 266280
MIBSPI1 7 VCLK Dual port 33440
MIBSPI3 8 VCLK Dual port 33440
MIBSPI5 9 VCLK Dual port 33440
VIM 10 VCLK Dual port 12560
MIBADC1 11 VCLK Dual port 4200
DMA 12 HCLK Dual port 18960
N2HET1 13 VCLK Dual port 31680
HET TU1 14 VCLK Dual port 6480
MIBADC2 18 VCLK Dual port 4200
N2HET2 19 VCLK Dual port 31680
HET TU2 20 VCLK Dual port 6480
ESRAM5(3) 21 HCLK Single port 266280
Several memory testing algorithms are stored in the PBIST ROM. However, TI recommends the March13N algorithm for application testing of RAM.
ESRAM1: Address 0x08000000 - 0x0800FFFF
ESRAM5: Address 0x08010000 - 0x0801FFFF

The PBIST ROM clock frequency is limited to 100 MHz, if 100 MHz < HCLK <= HCLKmax, or HCLK, if HCLK <= 100 MHz.

The PBIST ROM clock is divided down from HCLK. The divider is selected by programming the ROM_DIV field of the Memory Self-Test Global Control Register (MSTGCR) at address 0xFFFFFF58.

On-Chip SRAM Auto Initialization

This microcontroller allows some of the on-chip memories to be initialized through the Memory Hardware Initialization mechanism in the system module. This hardware mechanism allows an application to program the memory arrays with error detection capability to a known state based on their error detection scheme (odd/even parity or ECC).

The MINITGCR register enables the memory initialization sequence, and the MSINENA register selects the memories that are to be initialized.

For more information on these registers, see the device-specific Technical Reference Manual.

The mapping of the different on-chip memories to the specific bits of the MSINENA registers is shown in Table 6-26.

Table 6-26 Memory Initialization

CONNECTING MODULE ADDRESS RANGE MSINENA REGISTER BIT #
BASE ADDRESS ENDING ADDRESS
RAM (PD#1) 0x08000000 0x0800FFFF 0(1)
RAM (RAM_PD#1) 0x08010000 0x0801FFFF 0(1)
MIBSPI5 RAM 0xFF0A0000 0xFF0BFFFF 12(2)
MIBSPI3 RAM 0xFF0C0000 0xFF0DFFFF 11(2)
MIBSPI1 RAM 0xFF0E0000 0xFF0FFFFF 7(2)
DCAN3 RAM 0xFF1A0000 0xFF1BFFFF 10
DCAN2 RAM 0xFF1C0000 0xFF1DFFFF 6
DCAN1 RAM 0xFF1E0000 0xFF1FFFFF 5
MIBADC2 RAM 0xFF3A0000 0xFF3BFFFF 14
MIBADC1 RAM 0xFF3E0000 0xFF3FFFFF 8
N2HET2 RAM 0xFF440000 0xFF45FFFF 15
N2HET1 RAM 0xFF460000 0xFF47FFFF 3
HET TU2 RAM 0xFF4C0000 0xFF4DFFFF 16
HET TU1 RAM 0xFF4E0000 0xFF4FFFFF 4
DMA RAM 0xFFF80000 0xFFF80FFF 1
VIM RAM 0xFFF82000 0xFFF82FFF 2
The TCM RAM wrapper has separate control bits to select the RAM power domain that is to be auto-initialized.
The MibSPIx modules perform an initialization of the transmit and receive RAMs as soon as the module is released from its local reset. This is independent of whether the application chooses to initialize the MibSPIx RAMs using the system module auto-initialization method. The MibSPIx module must be first brought out of its local reset to use the system module auto-initialization method.

Vectored Interrupt Manager

The vectored interrupt manager (VIM) provides hardware assistance for prioritizing and controlling the many interrupt sources present on this device. Interrupts are caused by events outside of the normal flow of program execution. Normally, these events require a timely response from the CPU; therefore, when an interrupt occurs, the CPU switches execution from the normal program flow to an interrupt service routine (ISR).

VIM Features

The VIM module has the following features:

  • Supports 128 interrupt channels.
    • Provides programmable priority and enable for interrupt request lines.
  • Provides a direct hardware dispatch mechanism for fastest IRQ dispatch.
  • Provides two software dispatch mechanisms when the CPU VIC port is not used.
    • Index interrupt
    • Register vectored interrupt
  • Parity protected vector interrupt table against soft errors.

Interrupt Request Assignments

Table 6-27 Interrupt Request Assignments

Modules Interrupt Sources Default VIM Interrupt Channel
ESM ESM High level interrupt (NMI) 0
Reserved Reserved 1
RTI RTI compare interrupt 0 2
RTI RTI compare interrupt 1 3
RTI RTI compare interrupt 2 4
RTI RTI compare interrupt 3 5
RTI RTI overflow interrupt 0 6
RTI RTI overflow interrupt 1 7
RTI RTI time-base interrupt 8
GIO GIO interrupt A 9
N2HET1 N2HET1 level 0 interrupt 10
HET TU1 HET TU1 level 0 interrupt 11
MIBSPI1 MIBSPI1 level 0 interrupt 12
LIN LIN level 0 interrupt 13
MIBADC1 MIBADC1 event group interrupt 14
MIBADC1 MIBADC1 software group 1 interrupt 15
DCAN1 DCAN1 level 0 interrupt 16
SPI2 SPI2 level 0 interrupt 17
Reserved Reserved 18
CRC CRC Interrupt 19
ESM ESM low-level interrupt 20
SYSTEM Software interrupt (SSI) 21
CPU PMU Interrupt 22
GIO GIO interrupt B 23
N2HET1 N2HET1 level 1 interrupt 24
HET TU1 HET TU1 level 1 interrupt 25
MIBSPI1 MIBSPI1 level 1 interrupt 26
LIN LIN level 1 interrupt 27
MIBADC1 MIBADC1 software group 2 interrupt 28
DCAN1 DCAN1 level 1 interrupt 29
SPI2 SPI2 level 1 interrupt 30
MIBADC1 MIBADC1 magnitude compare interrupt 31
Reserved Reserved 32
DMA FTCA interrupt 33
DMA LFSA interrupt 34
DCAN2 DCAN2 level 0 interrupt 35
MIBSPI3 MIBSPI3 level 0 interrupt 37
MIBSPI3 MIBSPI3 level 1 interrupt 38
DMA HBCA interrupt 39
DMA BTCA interrupt 40
Reserved Reserved 41
DCAN2 DCAN2 level 1 interrupt 42
DCAN1 DCAN1 IF3 interrupt 44
DCAN3 DCAN3 level 0 interrupt 45
DCAN2 DCAN2 IF3 interrupt 46
FPU FPU interrupt 47
Reserved Reserved 48
SPI4 SPI4 level 0 interrupt 49
MIBADC2 MibADC2 event group interrupt 50
MIBADC2 MibADC2 software group1 interrupt 51
Reserved Reserved 52
MIBSPI5 MIBSPI5 level 0 interrupt 53
SPI4 SPI4 level 1 interrupt 54
DCAN3 DCAN3 level 1 interrupt 55
MIBSPI5 MIBSPI5 level 1 interrupt 56
MIBADC2 MibADC2 software group2 interrupt 57
Reserved Reserved 58
MIBADC2 MibADC2 magnitude compare interrupt 59
DCAN3 DCAN3 IF3 interrupt 60
FMC FSM_DONE interrupt 61
Reserved Reserved 62
N2HET2 N2HET2 level 0 interrupt 63
SCI SCI level 0 interrupt 64
HET TU2 HET TU2 level 0 interrupt 65
I2C I2C level 0 interrupt 66
Reserved Reserved 67–72
N2HET2 N2HET2 level 1 interrupt 73
SCI SCI level 1 interrupt 74
HET TU2 HET TU2 level 1 interrupt 75
Reserved Reserved 76–79
HWAG1 HWA_INT_REQ_H 80
HWAG2 HWA_INT_REQ_H 81
DCC1 DCC done interrupt 82
DCC2 DCC2 done interrupt 83
Reserved Reserved 84
PBIST Controller PBIST Done Interrupt 85
Reserved Reserved 86-87
HWAG1 HWA_INT_REQ_L 88
HWAG2 HWA_INT_REQ_L 89
ePWM1INTn ePWM1 Interrupt 90
ePWM1TZINTn ePWM1 Trip Zone Interrupt 91
ePWM2INTn ePWM2 Interrupt 92
ePWM2TZINTn ePWM2 Trip Zone Interrupt 93
ePWM3INTn ePWM3 Interrupt 94
ePWM3TZINTn ePWM3 Trip Zone Interrupt 95
ePWM4INTn ePWM4 Interrupt 96
ePWM4TZINTn ePWM4 Trip Zone Interrupt 97
ePWM5INTn ePWM5 Interrupt 98
ePWM5TZINTn ePWM5 Trip Zone Interrupt 99
ePWM6INTn ePWM6 Interrupt 100
ePWM6TZINTn ePWM6 Trip Zone Interrupt 101
ePWM7INTn ePWM7 Interrupt 102
ePWM7TZINTn ePWM7 Trip Zone Interrupt 103
eCAP1INTn eCAP1 Interrupt 104
eCAP2INTn eCAP2 Interrupt 105
eCAP3INTn eCAP3 Interrupt 106
eCAP4INTn eCAP4 Interrupt 107
eCAP5INTn eCAP5 Interrupt 108
eCAP6INTn eCAP6 Interrupt 109
eQEP1INTn eQEP1 Interrupt 110
eQEP2INTn eQEP2 Interrupt 111
Reserved Reserved 112–127

NOTE

Address location 0x00000000 in the VIM RAM is reserved for the phantom interrupt ISR entry; therefore only request channels 0..126 can be used and are offset by one address in the VIM RAM.

NOTE

The lower-order interrupt channels are higher priority channels than the higher-order interrupt channels.

NOTE

The application can change the mapping of interrupt sources to the interrupt channels through the interrupt channel control registers (CHANCTRLx) inside the VIM module.

DMA Controller

The DMA controller is used to transfer data between two locations in the memory map in the background of CPU operations. Typically, the DMA is used to:

  • Transfer blocks of data between external and internal data memories
  • Restructure portions of internal data memory
  • Continually service a peripheral

DMA Features

  • CPU independent data transfer
  • One 64-bit master port that interfaces to the RM4x Memory System.
  • FIFO buffer (four entries deep and each 64 bits wide)
  • Channel control information is stored in RAM protected by parity
  • 16 channels with individual enable
  • Channel chaining capability
  • 32 peripheral DMA requests
  • Hardware and software DMA requests
  • 8-, 16-, 32- or 64-bit transactions supported
  • Multiple addressing modes for source/destination (fixed, increment, offset)
  • Auto-initiation
  • Power-management mode
  • Memory Protection with four configurable memory regions

Default DMA Request Map

The DMA module on this microcontroller has 16 channels and up to 32 hardware DMA requests. The module contains DREQASIx registers which are used to map the DMA requests to the DMA channels. By default, channel 0 is mapped to request 0, channel 1 to request 1, and so on.

Some DMA requests have multiple sources, as shown in Table 6-28. The application must ensure that only one of these DMA request sources is enabled at any time.

Table 6-28 DMA Request Line Connection

Modules DMA Request Sources DMA Request
MIBSPI1 MIBSPI1[1](1) DMAREQ[0]
MIBSPI1 MIBSPI1[0](2) DMAREQ[1]
SPI2 SPI2 receive DMAREQ[2]
SPI2 SPI2 transmit DMAREQ[3]
MIBSPI1 / MIBSPI3 / DCAN2 MIBSPI1[2] / MIBSPI3[2] / DCAN2 IF3 DMAREQ[4]
MIBSPI1 / MIBSPI3 / DCAN2 MIBSPI1[3] / MIBSPI3[3] / DCAN2 IF2 DMAREQ[5]
DCAN1 / MIBSPI5 DCAN1 IF2 / MIBSPI5[2] DMAREQ[6]
MIBADC1 / MIBSPI5 MIBADC1 event / MIBSPI5[3] DMAREQ[7]
MIBSPI1 / MIBSPI3 / DCAN1 MIBSPI1[4] / MIBSPI3[4] / DCAN1 IF1 DMAREQ[8]
MIBSPI1 / MIBSPI3 / DCAN2 MIBSPI1[5] / MIBSPI3[5] / DCAN2 IF1 DMAREQ[9]
MIBADC1 / I2C / MIBSPI5 MIBADC1 G1 / I2C receive / MIBSPI5[4] DMAREQ[10]
MIBADC1 / I2C / MIBSPI5 MIBADC1 G2 / I2C transmit / MIBSPI5[5] DMAREQ[11]
RTI / MIBSPI1 / MIBSPI3 RTI DMAREQ0 / MIBSPI1[6] / MIBSPI3[6] DMAREQ[12]
RTI / MIBSPI1 / MIBSPI3 RTI DMAREQ1 / MIBSPI1[7] / MIBSPI3[7] DMAREQ[13]
MIBSPI3 / MibADC2 / MIBSPI5 MIBSPI3[1](1) / MibADC2 event / MIBSPI5[6] DMAREQ[14]
MIBSPI3 / MIBSPI5 MIBSPI3[0](2) / MIBSPI5[7] DMAREQ[15]
MIBSPI1 / MIBSPI3 / DCAN1 / MibADC2 MIBSPI1[8] / MIBSPI3[8] / DCAN1 IF3 / MibADC2 G1 DMAREQ[16]
MIBSPI1 / MIBSPI3 / DCAN3 / MibADC2 MIBSPI1[9] / MIBSPI3[9] / DCAN3 IF1 / MibADC2 G2 DMAREQ[17]
RTI / MIBSPI5 RTI DMAREQ2 / MIBSPI5[8] DMAREQ[18]
RTI / MIBSPI5 RTI DMAREQ3 / MIBSPI5[9] DMAREQ[19]
N2HET1 / N2HET2 / DCAN3 N2HET1 DMAREQ[4] / N2HET2 DMAREQ[4] / DCAN3 IF2 DMAREQ[20]
N2HET1 / N2HET2 / DCAN3 N2HET1 DMAREQ[5] / N2HET2 DMAREQ[5] / DCAN3 IF3 DMAREQ[21]
MIBSPI1 / MIBSPI3 / MIBSPI5 MIBSPI1[10] / MIBSPI3[10] / MIBSPI5[10] DMAREQ[22]
MIBSPI1 / MIBSPI3 / MIBSPI5 MIBSPI1[11] / MIBSPI3[11] / MIBSPI5[11] DMAREQ[23]
N2HET1 / N2HET2 / SPI4 / MIBSPI5 N2HET1 DMAREQ[6] / N2HET2 DMAREQ[6] / SPI4 receive / MIBSPI5[12] DMAREQ[24]
N2HET1 / N2HET2 / SPI4 / MIBSPI5 N2HET1 DMAREQ[7] / N2HET2 DMAREQ[7] / SPI4 transmit / MIBSPI5[13] DMAREQ[25]
CRC / MIBSPI1 / MIBSPI3 CRC DMAREQ[0] / MIBSPI1[12] / MIBSPI3[12] DMAREQ[26]
CRC / MIBSPI1 / MIBSPI3 CRC DMAREQ[1] / MIBSPI1[13] / MIBSPI3[13] DMAREQ[27]
LIN / MIBSPI5 LIN receive / MIBSPI5[14] DMAREQ[28]
LIN / MIBSPI5 LIN transmit / MIBSPI5[15] DMAREQ[29]
MIBSPI1 / MIBSPI3 / SCI / MIBSPI5 MIBSPI1[14] / MIBSPI3[14] / SCI receive / MIBSPI5[1](1) DMAREQ[30]
MIBSPI1 / MIBSPI3 / SCI / MIBSPI5 MIBSPI1[15] / MIBSPI3[15] / SCI transmit / MIBSPI5[0](2) DMAREQ[31]
SPI1, SPI3, SPI5 receive when configured in standard SPI mode
SPI1, SPI3, SPI5 transmit when configured in standard SPI mode

Real-Time Interrupt Module

The real-time interrupt (RTI) module provides timer functionality for operating systems and for benchmarking code. The RTI module can incorporate several counters that define the time bases needed for scheduling an operating system.

The timers also let you benchmark certain areas of code by reading the values of the counters at the beginning and the end of the desired code range and calculating the difference between the values.

Features

The RTI module has the following features:

  • Two independent 64-bit counter blocks
  • Four configurable compares for generating operating system ticks or DMA requests. Each event can be driven by either counter block 0 or counter block 1.
  • Fast enabling/disabling of events
  • Two timestamp (capture) functions for system or peripheral interrupts, one for each counter block

Block Diagrams

Figure 6-11 shows a high-level block diagram for one of the two 64-bit counter blocks inside the RTI module. Both the counter blocks are identical except the Network Time Unit (NTUx) inputs are only available as time-base inputs for the counter block 0. Figure 6-12 shows the compare unit block diagram of the RTI module.

RM44L920 RM44L520 rti_counter_bd_pns160.gif Figure 6-11 Counter Block Diagram
RM44L920 RM44L520 rti_compare_bd_pns160.gif Figure 6-12 Compare Block Diagram

Clock Source Options

The RTI module uses the RTI1CLK clock domain for generating the RTI time bases.

The application can select the clock source for the RTI1CLK by configuring the RCLKSRC register in the system module at address 0xFFFFFF50. The default source for RTI1CLK is VCLK.

For more information on clock sources, see Table 6-8 and Table 6-13.

Network Time Synchronization Inputs

The RTI module supports four Network Time Unit (NTU) inputs that signal internal system events, and which can be used to synchronize the time base used by the RTI module. On this device, these NTU inputs are connected as shown in Table 6-29.

Table 6-29 Network Time Synchronization Inputs

NTU INPUT SOURCE
0 Reserved
1 Reserved
2 Reserved
3 EXTCLKIN1 clock input

Error Signaling Module

The Error Signaling Module (ESM) manages the various error conditions on the RM44Lx20 microcontroller. The error condition is handled based on a fixed severity level assigned to it. Any severe error condition can be configured to drive a low level on a dedicated device terminal called nERROR. The nERROR can be used as an indicator to an external monitor circuit to put the system into a safe state.

ESM Features

The features of the ESM are:

  • 128 interrupt/error channels are supported, divided into three groups
    • 64 channels with maskable interrupt and configurable error pin behavior
    • 32 error channels with nonmaskable interrupt and predefined error pin behavior
    • 32 channels with predefined error pin behavior only
  • Error pin to signal severe device failure
  • Configurable time base for error signal
  • Error forcing capability

ESM Channel Assignments

The ESM integrates all the device error conditions and groups them in the order of severity. Group1 is used for errors of the lowest severity while Group3 is used for errors of the highest severity. The device response to each error is determined by the severity group it is connected to. Table 6-31 lists the channel assignment for each group.

Table 6-30 ESM Groups

ERROR GROUP INTERRUPT CHARACTERISTICS INFLUENCE ON ERROR
TERMINAL
Group1 Maskable, low or high priority Configurable
Group2 Nonmaskable, high priority Fixed
Group3 No interrupt generated Fixed

Table 6-31 ESM Channel Assignments

ERROR CONDITION GROUP CHANNELS
Group1
Reserved Group1 0
MibADC2 - RAM parity error Group1 1
DMA - MPU configuration violation Group1 2
DMA - control packet RAM parity error Group1 3
Reserved Group1 4
DMA - error on DMA read access, imprecise error Group1 5
FMC - correctable ECC error: bus1 and bus2 interfaces
(does not include accesses to Bank 7)
Group1 6
N2HET1 - RAM parity error Group1 7
HET TU1/HET TU2 - dual-control packet RAM parity error Group1 8
HET TU1/HET TU2 - MPU configuration violation Group1 9
PLL1 - Slip Group1 10
Clock Monitor - oscillator fail Group1 11
Reserved Group1 12
DMA - error on DMA write access, imprecise error Group1 13
Reserved Group1 14
VIM RAM - parity error Group1 15
Reserved Group1 16
MibSPI1 - RAM parity error Group1 17
MibSPI3 - RAM parity error Group1 18
MibADC1 - RAM parity error Group1 19
Reserved Group1 20
DCAN1 - RAM parity error Group1 21
DCAN3 - RAM parity error Group1 22
DCAN2 - RAM parity error Group1 23
MibSPI5 - RAM parity error Group1 24
Reserved Group1 25
RAM even bank (B0TCM) - correctable ECC error Group1 26
CPU - self-test failed Group1 27
RAM odd bank (B1TCM) - correctable ECC error Group1 28
Reserved Group1 29
DCC1 - error Group1 30
CCM-R4 - self-test failed Group1 31
Reserved Group1 32
Reserved Group1 33
N2HET2 - RAM parity error Group1 34
FMC - correctable ECC error (Bank 7 access) Group1 35
FMC - uncorrectable ECC error (Bank 7 access) Group1 36
IOMM - Access to unimplemented location in IOMM frame, or write access detected in unprivileged mode Group1 37
Power domain controller compare error Group1 38
Power domain controller self-test error Group1 39
eFuse Controller Error – this error signal is generated when any bit in the eFuse controller error status register is set. The application can choose to generate an interrupt whenever this bit is set to service any eFuse controller error conditions. Group1 40
eFuse Controller - Self-Test Error. This error signal is generated only when a self-test on the eFuse controller generates an error condition. When an ECC self-test error is detected, group 1 channel 40 error signal will also be set. Group1 41
Reserved Group1 42
Reserved Group1 43
Reserved Group1 44
Reserved Group1 45
Reserved Group1 46
Reserved Group1 47
Reserved Group1 48
Reserved Group1 49
Reserved Group1 50
Reserved Group1 51
Reserved Group1 52
Reserved Group1 53
Reserved Group1 54
Reserved Group1 55
Reserved Group1 56
Reserved Group1 57
Reserved Group1 58
Reserved Group1 59
Reserved Group1 60
Reserved Group1 61
DCC2 - error Group1 62
Reserved Group1 63
Group2
Reserved Group2 0
Reserved Group2 1
CCMR4 - dual-CPU lock-step error Group2 2
Reserved Group2 3
FMC - uncorrectable address parity error on accesses to main flash Group2 4
Reserved Group2 5
RAM even bank (B0TCM) - uncorrectable redundant address decode error Group2 6
Reserved Group2 7
RAM odd bank (B1TCM) - uncorrectable redundant address decode error Group2 8
Reserved Group2 9
RAM even bank (B0TCM) - address bus parity error Group2 10
Reserved Group2 11
RAM odd bank (B1TCM) - address bus parity error Group2 12
Reserved Group2 13
Reserved Group2 14
Reserved Group2 15
TCM - ECC live lock detect Group2 16
Reserved Group2 17
Reserved Group2 18
Reserved Group2 19
Reserved Group2 20
Reserved Group2 21
Reserved Group2 22
Reserved Group2 23
Windowed Watchdog (WWD) violation Group2 24
Reserved Group2 25
Reserved Group2 26
Reserved Group2 27
Reserved Group2 28
Reserved Group2 29
Reserved Group2 30
Reserved Group2 31
Group3
Reserved Group3 0
eFuse Farm - autoload error Group3 1
Reserved Group3 2
RAM even bank (B0TCM) - ECC uncorrectable error Group3 3
Reserved Group3 4
RAM odd bank (B1TCM) - ECC uncorrectable error Group3 5
Reserved Group3 6
FMC - uncorrectable ECC error: bus1 and bus2 interfaces
(does not include address parity error and errors on accesses to Bank 7)
Group3 7
Reserved Group3 8
Reserved Group3 9
Reserved Group3 10
Reserved Group3 11
Reserved Group3 12
Reserved Group3 13
Reserved Group3 14
Reserved Group3 15
Reserved Group3 16
Reserved Group3 17
Reserved Group3 18
Reserved Group3 19
Reserved Group3 20
Reserved Group3 21
Reserved Group3 22
Reserved Group3 23
Reserved Group3 24
Reserved Group3 25
Reserved Group3 26
Reserved Group3 27
Reserved Group3 28
Reserved Group3 29
Reserved Group3 30
Reserved Group3 31

Reset/Abort/Error Sources

Table 6-32 Reset/Abort/Error Sources

ERROR SOURCE CPUMODE ERROR RESPONSE ESM HOOKUP
GROUP.CHANNEL
CPU TRANSACTIONS
Precise write error (NCNB/Strongly Ordered) User/Privilege Precise Abort (CPU) N/A
Precise read error (NCB/Device or Normal) User/Privilege Precise Abort (CPU) N/A
Imprecise write error (NCB/Device or Normal) User/Privilege Imprecise Abort (CPU) N/A
Illegal instruction User/Privilege Undefined Instruction Trap (CPU)(1) N/A
MPU access violation User/Privilege Abort (CPU) N/A
SRAM
B0 TCM (even) ECC single error (correctable) User/Privilege ESM 1.26
B0 TCM (even) ECC double error (uncorrectable) User/Privilege Abort (CPU), ESM => → nERROR 3.3
B0 TCM (even) uncorrectable error (that is, redundant address decode) User/Privilege ESM => NMI => nERROR 2.6
B0 TCM (even) address bus parity error User/Privilege ESM => NMI => nERROR 2.10
B1 TCM (odd) ECC single error (correctable) User/Privilege ESM 1.28
B1 TCM (odd) ECC double error (uncorrectable) User/Privilege Abort (CPU), ESM => nERROR 3.5
B1 TCM (odd) uncorrectable error (that is, redundant address decode) User/Privilege ESM => NMI => nERROR 2.8
B1 TCM (odd) address bus parity error User/Privilege ESM => NMI => nERROR 2.12
FLASH WITH CPU BASED ECC
FMC correctable error - Bus1 and Bus2 interfaces (does not include accesses to Bank 7) User/Privilege ESM 1.6
FMC uncorrectable error - Bus1 and Bus2 accesses
(does not include address parity error)
User/Privilege Abort (CPU), ESM => nERROR 3.7
FMC uncorrectable error - address parity error on Bus1 accesses User/Privilege ESM => NMI => nERROR 2.4
FMC correctable error - Accesses to Bank 7 User/Privilege ESM 1.35
FMC uncorrectable error - Accesses to Bank 7 User/Privilege ESM 1.36
DMA TRANSACTIONS
External imprecise error on read (Illegal transaction with ok response) User/Privilege ESM 1.5
External imprecise error on write (Illegal transaction with ok response) User/Privilege ESM 1.13
Memory access permission violation User/Privilege ESM 1.2
Memory parity error User/Privilege ESM 1.3
HET TU1 (HTU1)
NCNB (Strongly Ordered) transaction with slave error response User/Privilege Interrupt => VIM N/A
External imprecise error (Illegal transaction with ok response) User/Privilege Interrupt => VIM N/A
Memory access permission violation User/Privilege ESM 1.9
Memory parity error User/Privilege ESM 1.8
HET TU2 (HTU2)
NCNB (Strongly Ordered) transaction with slave error response User/Privilege Interrupt => VIM N/A
External imprecise error (Illegal transaction with ok response) User/Privilege Interrupt => VIM N/A
Memory access permission violation User/Privilege ESM 1.9
Memory parity error User/Privilege ESM 1.8
N2HET1
Memory parity error User/Privilege ESM 1.7
N2HET2
Memory parity error User/Privilege ESM 1.34
MIBSPI
MibSPI1 memory parity error User/Privilege ESM 1.17
MibSPI3 memory parity error User/Privilege ESM 1.18
MibSPI5 memory parity error User/Privilege ESM 1.24
MIBADC
MibADC1 memory parity error User/Privilege ESM 1.19
MibADC2 memory parity error User/Privilege ESM 1.1
DCAN
DCAN1 memory parity error User/Privilege ESM 1.21
DCAN2 memory parity error User/Privilege ESM 1.23
DCAN3 memory parity error User/Privilege ESM 1.22
PLL
PLL slip error User/Privilege ESM 1.10
CLOCK MONITOR
Clock monitor interrupt User/Privilege ESM 1.11
DCC
DCC1 error User/Privilege ESM 1.30
DCC2 error User/Privilege ESM 1.62
CCM-R4
Self-test failure User/Privilege ESM 1.31
Compare failure User/Privilege ESM => NMI => nERROR 2.2
VIM
Memory parity error User/Privilege ESM 1.15
VOLTAGE MONITOR
VMON out of voltage range N/A Reset N/A
CPU SELF-TEST (LBIST)
Cortex-R4F CPU self-test (LBIST) error User/Privilege ESM 1.27
PIN MULTIPLEXING CONTROL
Mux configuration error User/Privilege ESM 1.37
POWER DOMAIN CONTROL
PSCON compare error User/Privilege ESM 1.38
PSCON self-test error User/Privilege ESM 1.39
eFuse CONTROLLER
eFuse Controller Autoload error User/Privilege ESM => nERROR 3.1
eFuse Controller - Any bit set in the error status register User/Privilege ESM 1.40
eFuse Controller self-test error User/Privilege ESM 1.41
WINDOWED WATCHDOG
WWD Nonmaskable Interrupt exception N/A ESM => NMI => nERROR 2.24
ERRORS REFLECTED IN THE SYSESR REGISTER
Power-Up Reset N/A Reset N/A
Oscillator fail / PLL slip(2) N/A Reset N/A
Watchdog exception N/A Reset N/A
CPU Reset (driven by the CPU STC) N/A Reset N/A
Software Reset N/A Reset N/A
External Reset N/A Reset N/A
The Undefined Instruction TRAP is not detectable outside the CPU. The trap is taken only if the instruction reaches the execute stage of the CPU.
Oscillator fail/PLL slip can be configured in the system register (SYS.PLLCTL1) to generate a reset.

Digital Windowed Watchdog

This device includes a Digital Windowed Watchdog (DWWD) module that protects against runaway code execution (see Figure 6-13).

The DWWD module allows the application to configure the time window within which the DWWD module expects the application to service the watchdog. A watchdog violation occurs if the application services the watchdog outside of this window, or fails to service the watchdog at all. The application can choose to generate a system reset or an ESM group2 error signal in case of a watchdog violation.

The watchdog is disabled by default and must be enabled by the application. Once enabled, the watchdog can only be disabled upon a system reset.

RM44L920 RM44L520 rti_dwwd.gif Figure 6-13 Digital Windowed Watchdog Example

Debug Subsystem

Block Diagram

The device contains an ICEPICK module (version C) to allow JTAG access to the scan chains (see Figure 6-14).

RM44L920 RM44L520 debug_subsystem_spns225.gif Figure 6-14 Debug Subsystem Block Diagram

Debug Components Memory Map

Table 6-33 Debug Components Memory Map

MODULE
NAME
FRAME CHIP
SELECT
FRAME ADDRESS RANGE FRAME
SIZE
ACTUAL
SIZE
RESPONSE FOR ACCESS TO
UNIMPLEMENTED LOCATIONS
IN FRAME
START END
CoreSight Debug ROM CSCS0 0xFFA0_0000 0xFFA0_0FFF 4KB 4KB Reads return zeros, writes have no effect
Cortex-R4F Debug CSCS1 0xFFA0_1000 0xFFA0_1FFF 4KB 4KB Reads return zeros, writes have no effect

JTAG Identification Code

The JTAG ID code for this device is the same as the device ICEPick Identification Code. For the JTAG ID Code per silicon revision, see Table 6-34.

Table 6-34 JTAG ID Code

SILICON REVISION ID
Rev 0 0x0BB0302F
Rev A 0x1BB0302F

Debug ROM

The Debug ROM stores the location of the components on the Debug APB bus (see Table 6-35).

Table 6-35 Debug ROM Table

ADDRESS DESCRIPTION VALUE
0x000 Pointer to Cortex-R4F 0x0000 1003
0x001 Reserved 0x0000 2002
0x002 Reserved 0x0000 3002
0x003 Reserved 0x0000 4003
0x004 end of table 0x0000 0000

JTAG Scan Interface Timings

Table 6-36 JTAG Scan Interface Timing(1)

NO. PARAMETER MIN MAX UNIT
fTCK TCK frequency (at HCLKmax) 12 MHz
fRTCK RTCK frequency (at TCKmax and HCLKmax) 10 MHz
1 td(TCK -RTCK) Delay time, TCK to RTCK 24 ns
2 tsu(TDI/TMS - RTCKr) Setup time, TDI, TMS before RTCK rise (RTCKr) 26 ns
3 th(RTCKr -TDI/TMS) Hold time, TDI, TMS after RTCKr 0 ns
4 th(RTCKr -TDO) Hold time, TDO after RTCKf 0 ns
5 td(TCKf -TDO) Delay time, TDO valid after RTCK fall (RTCKf) 12 ns
Timings for TDO are specified for a maximum of 50-pF load on TDO.
RM44L920 RM44L520 jtag_timing_pns160.gif Figure 6-15 JTAG Timing

Advanced JTAG Security Module

This device includes a an Advanced JTAG Security Module (AJSM) module. The AJSM provides maximum security to the memory content of the device by letting users secure the device after programming.

RM44L920 RM44L520 ajsm_unlock_pns160.gif Figure 6-16 AJSM Unlock

The device is unsecure by default by virtue of a 128-bit visible unlock code programmed in the OTP address 0xF0000000. The OTP contents are XOR-ed with the contents of the "Unlock By Scan" register. The outputs of these XOR gates are again combined with a set of secret internal tie-offs. The output of this combinational logic is compared against a secret hard-wired 128-bit value. A match results in the UNLOCK signal being asserted, so that the device is now unsecure.

A user can secure the device by changing at least 1 bit in the visible unlock code from 1 to 0. Changing a 0 to 1 is not possible because the visible unlock code is stored in the One Time Programmable (OTP) flash region. Also, changing all 128 bits to zeros is not a valid condition and will permanently secure the device.

Once secured, a user can unsecure the device by scanning an appropriate value into the "Unlock By Scan" register of the AJSM module. This register is accessible by configuring an IR value of 0b1011 on the AJSM TAP. The value to be scanned is such that the XOR of the OTP contents and the Unlock-By-Scan register contents results in the original visible unlock code.

The Unlock-By-Scan register is reset only upon asserting power-on reset (nPORRST).

A secure device only permits JTAG accesses to the AJSM scan chain through the Secondary Tap 2 of the ICEPick module. All other secondary taps, test taps, and the boundary scan interface are not accessible in this state.

Boundary Scan Chain

The device supports BSDL-compliant boundary scan for testing pin-to-pin compatibility. The boundary scan chain is connected to the Boundary Scan Interface of the ICEPICK module (see Figure 6-17).

RM44L920 RM44L520 boundary_scan_implementation _pns160.gif Figure 6-17 Boundary Scan Implementation (Conceptual Diagram)

Data is serially shifted into all boundary-scan buffers through TDI, and out through TDO.