SBASA14 May   2020 PCMD3180

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Simplified Block Diagram
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Timing Requirements: I2C Interface
    7. 6.7  Switching Characteristics: I2C Interface
    8. 6.8  Timing Requirements: SPI Interface
    9. 6.9  Switching Characteristics: SPI Interface
    10. 6.10 Timing Requirements: TDM, I2S or LJ Interface
    11. 6.11 Switching Characteristics: TDM, I2S or LJ Interface
    12. 6.12 Timing Requirements: PDM Digital Microphone Interface
    13. 6.13 Switching Characteristics: PDM Digial Microphone Interface
    14. 6.14 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Serial Interfaces
        1. 7.3.1.1 Control Serial Interfaces
        2. 7.3.1.2 Audio Serial Interfaces
          1. 7.3.1.2.1 Time Division Multiplexed Audio (TDM) Interface
          2. 7.3.1.2.2 Inter IC Sound (I2S) Interface
          3. 7.3.1.2.3 Left-Justified (LJ) Interface
        3. 7.3.1.3 Using Multiple Devices With Shared Buses
      2. 7.3.2 Phase-Locked Loop (PLL) and Clock Generation
      3. 7.3.3 Reference Voltage
      4. 7.3.4 Microphone Bias
      5. 7.3.5 Digital PDM Microphone Record Channel
      6. 7.3.6 Signal-Chain Processing
        1. 7.3.6.1 Programmable Digital Volume Control
        2. 7.3.6.2 Programmable Channel Gain Calibration
        3. 7.3.6.3 Programmable Channel Phase Calibration
        4. 7.3.6.4 Programmable Digital High-Pass Filter
        5. 7.3.6.5 Programmable Digital Biquad Filters
        6. 7.3.6.6 Programmable Channel Summer and Digital Mixer
        7. 7.3.6.7 Configurable Digital Decimation Filters
          1. 7.3.6.7.1 Linear Phase Filters
            1. 7.3.6.7.1.1 Sampling Rate: 8 kHz or 7.35 kHz
            2. 7.3.6.7.1.2 Sampling Rate: 16 kHz or 14.7 kHz
            3. 7.3.6.7.1.3 Sampling Rate: 24 kHz or 22.05 kHz
            4. 7.3.6.7.1.4 Sampling Rate: 32 kHz or 29.4 kHz
            5. 7.3.6.7.1.5 Sampling Rate: 48 kHz or 44.1 kHz
            6. 7.3.6.7.1.6 Sampling Rate: 96 kHz or 88.2 kHz
            7. 7.3.6.7.1.7 Sampling Rate: 192 kHz or 176.4 kHz
            8. 7.3.6.7.1.8 Sampling Rate: 384 kHz or 352.8 kHz
            9. 7.3.6.7.1.9 Sampling Rate 768 kHz or 705.6 kHz
          2. 7.3.6.7.2 Low-Latency Filters
            1. 7.3.6.7.2.1 Sampling Rate: 16 kHz or 14.7 kHz
            2. 7.3.6.7.2.2 Sampling Rate: 24 kHz or 22.05 kHz
            3. 7.3.6.7.2.3 Sampling Rate: 32 kHz or 29.4 kHz
            4. 7.3.6.7.2.4 Sampling Rate: 48 kHz or 44.1 kHz
            5. 7.3.6.7.2.5 Sampling Rate: 96 kHz or 88.2 kHz
            6. 7.3.6.7.2.6 Sampling Rate 192 kHz or 176.4 kHz
          3. 7.3.6.7.3 Ultra-Low-Latency Filters
            1. 7.3.6.7.3.1 Sampling Rate: 16 kHz or 14.7 kHz
            2. 7.3.6.7.3.2 Sampling Rate: 24 kHz or 22.05 kHz
            3. 7.3.6.7.3.3 Sampling Rate: 32 kHz or 29.4 kHz
            4. 7.3.6.7.3.4 Sampling Rate: 48 kHz or 44.1 kHz
            5. 7.3.6.7.3.5 Sampling Rate: 96 kHz or 88.2 kHz
            6. 7.3.6.7.3.6 Sampling Rate 192 kHz or 176.4 kHz
            7. 7.3.6.7.3.7 Sampling Rate 384 kHz or 352.8 kHz
      7. 7.3.7 Interrupts, Status, and Digital I/O Pin Multiplexing
    4. 7.4 Device Functional Modes
      1. 7.4.1 Hardware Shutdown
      2. 7.4.2 Sleep Mode or Software Shutdown
      3. 7.4.3 Active Mode
      4. 7.4.4 Software Reset
    5. 7.5 Programming
      1. 7.5.1 Control Serial Interfaces
        1. 7.5.1.1 I2C Control Interface
          1. 7.5.1.1.1 General I2C Operation
          2. 7.5.1.1.2 I2C Single-Byte and Multiple-Byte Transfers
            1. 7.5.1.1.2.1 I2C Single-Byte Write
            2. 7.5.1.1.2.2 I2C Multiple-Byte Write
            3. 7.5.1.1.2.3 I2C Single-Byte Read
            4. 7.5.1.1.2.4 I2C Multiple-Byte Read
        2. 7.5.1.2 SPI Control Interface
          1. Table 1. SPI Command Word
    6. 7.6 Register Maps
      1. 7.6.1 Device Configuration Registers
        1. 7.6.1.1 Register Summary Table Page=0x00
        2. 7.6.1.2 Register Descriptions
          1. 7.6.1.2.1  PAGE_CFG Register (page = 0x00, address = 0x00) [reset = 0h]
            1. Table 45. PAGE_CFG Register Field Descriptions
          2. 7.6.1.2.2  SW_RESET Register (page = 0x00, address = 0x01) [reset = 0h]
            1. Table 46. SW_RESET Register Field Descriptions
          3. 7.6.1.2.3  SLEEP_CFG Register (page = 0x00, address = 0x02) [reset = 0h]
            1. Table 47. SLEEP_CFG Register Field Descriptions
          4. 7.6.1.2.4  SHDN_CFG Register (page = 0x00, address = 0x05) [reset = 5h]
            1. Table 48. SHDN_CFG Register Field Descriptions
          5. 7.6.1.2.5  ASI_CFG0 Register (page = 0x00, address = 0x07) [reset = 30h]
            1. Table 49. ASI_CFG0 Register Field Descriptions
          6. 7.6.1.2.6  ASI_CFG1 Register (page = 0x00, address = 0x08) [reset = 0h]
            1. Table 50. ASI_CFG1 Register Field Descriptions
          7. 7.6.1.2.7  ASI_CFG2 Register (page = 0x00, address = 0x09) [reset = 0h]
            1. Table 51. ASI_CFG2 Register Field Descriptions
          8. 7.6.1.2.8  ASI_CH1 Register (page = 0x00, address = 0x0B) [reset = 0h]
            1. Table 52. ASI_CH1 Register Field Descriptions
          9. 7.6.1.2.9  ASI_CH2 Register (page = 0x00, address = 0x0C) [reset = 1h]
            1. Table 53. ASI_CH2 Register Field Descriptions
          10. 7.6.1.2.10 ASI_CH3 Register (page = 0x00, address = 0x0D) [reset = 2h]
            1. Table 54. ASI_CH3 Register Field Descriptions
          11. 7.6.1.2.11 ASI_CH4 Register (page = 0x00, address = 0x0E) [reset = 3h]
            1. Table 55. ASI_CH4 Register Field Descriptions
          12. 7.6.1.2.12 ASI_CH5 Register (page = 0x00, address = 0x0F) [reset = 4h]
            1. Table 56. ASI_CH5 Register Field Descriptions
          13. 7.6.1.2.13 ASI_CH6 Register (page = 0x00, address = 0x10) [reset = 5h]
            1. Table 57. ASI_CH6 Register Field Descriptions
          14. 7.6.1.2.14 ASI_CH7 Register (page = 0x00, address = 0x11) [reset = 6h]
            1. Table 58. ASI_CH7 Register Field Descriptions
          15. 7.6.1.2.15 ASI_CH8 Register (page = 0x00, address = 0x12) [reset = 7h]
            1. Table 59. ASI_CH8 Register Field Descriptions
          16. 7.6.1.2.16 MST_CFG0 Register (page = 0x00, address = 0x13) [reset = 2h]
            1. Table 60. MST_CFG0 Register Field Descriptions
          17. 7.6.1.2.17 MST_CFG1 Register (page = 0x00, address = 0x14) [reset = 48h]
            1. Table 61. MST_CFG1 Register Field Descriptions
          18. 7.6.1.2.18 ASI_STS Register (page = 0x00, address = 0x15) [reset = FFh]
            1. Table 62. ASI_STS Register Field Descriptions
          19. 7.6.1.2.19 CLK_SRC Register (page = 0x00, address = 0x16) [reset = 10h]
            1. Table 63. CLK_SRC Register Field Descriptions
          20. 7.6.1.2.20 PDMCLK_CFG Register (page = 0x00, address = 0x1F) [reset = 40h]
            1. Table 64. PDMCLK_CFG Register Field Descriptions
          21. 7.6.1.2.21 PDMIN_CFG Register (page = 0x00, address = 0x20) [reset = 0h]
            1. Table 65. PDMIN_CFG Register Field Descriptions
          22. 7.6.1.2.22 GPIO_CFG0 Register (page = 0x00, address = 0x21) [reset = 22h]
            1. Table 66. GPIO_CFG0 Register Field Descriptions
          23. 7.6.1.2.23 GPO_CFG0 Register (page = 0x00, address = 0x22) [reset = 0h]
            1. Table 67. GPO_CFG0 Register Field Descriptions
          24. 7.6.1.2.24 GPO_CFG1 Register (page = 0x00, address = 0x23) [reset = 0h]
            1. Table 68. GPO_CFG1 Register Field Descriptions
          25. 7.6.1.2.25 GPO_CFG2 Register (page = 0x00, address = 0x24) [reset = 0h]
            1. Table 69. GPO_CFG2 Register Field Descriptions
          26. 7.6.1.2.26 GPO_CFG3 Register (page = 0x00, address = 0x25) [reset = 0h]
            1. Table 70. GPO_CFG3 Register Field Descriptions
          27. 7.6.1.2.27 GPO_VAL Register (page = 0x00, address = 0x29) [reset = 0h]
            1. Table 71. GPO_VAL Register Field Descriptions
          28. 7.6.1.2.28 GPIO_MON Register (page = 0x00, address = 0x2A) [reset = 0h]
            1. Table 72. GPIO_MON Register Field Descriptions
          29. 7.6.1.2.29 GPI_CFG0 Register (page = 0x00, address = 0x2B) [reset = 0h]
            1. Table 73. GPI_CFG0 Register Field Descriptions
          30. 7.6.1.2.30 GPI_CFG1 Register (page = 0x00, address = 0x2C) [reset = 0h]
            1. Table 74. GPI_CFG1 Register Field Descriptions
          31. 7.6.1.2.31 GPI_MON Register (page = 0x00, address = 0x2F) [reset = 0h]
            1. Table 75. GPI_MON Register Field Descriptions
          32. 7.6.1.2.32 INT_CFG Register (page = 0x00, address = 0x32) [reset = 0h]
            1. Table 76. INT_CFG Register Field Descriptions
          33. 7.6.1.2.33 INT_MASK0 Register (page = 0x00, address = 0x33) [reset = FFh]
            1. Table 77. INT_MASK0 Register Field Descriptions
          34. 7.6.1.2.34 INT_LTCH0 Register (page = 0x00, address = 0x36) [reset = 0h]
            1. Table 78. INT_LTCH0 Register Field Descriptions
          35. 7.6.1.2.35 BIAS_CFG Register (page = 0x00, address = 0x3B) [reset = 0h]
            1. Table 79. BIAS_CFG Register Field Descriptions
          36. 7.6.1.2.36 CH1_CFG0 Register (page = 0x00, address = 0x3C) [reset = 0h]
            1. Table 80. CH1_CFG0 Register Field Descriptions
          37. 7.6.1.2.37 CH1_CFG2 Register (page = 0x00, address = 0x3E) [reset = C9h]
            1. Table 81. CH1_CFG2 Register Field Descriptions
          38. 7.6.1.2.38 CH1_CFG3 Register (page = 0x00, address = 0x3F) [reset = 80h]
            1. Table 82. CH1_CFG3 Register Field Descriptions
          39. 7.6.1.2.39 CH1_CFG4 Register (page = 0x00, address = 0x40) [reset = 0h]
            1. Table 83. CH1_CFG4 Register Field Descriptions
          40. 7.6.1.2.40 CH2_CFG0 Register (page = 0x00, address = 0x41) [reset = 0h]
            1. Table 84. CH2_CFG0 Register Field Descriptions
          41. 7.6.1.2.41 CH2_CFG2 Register (page = 0x00, address = 0x43) [reset = C9h]
            1. Table 85. CH2_CFG2 Register Field Descriptions
          42. 7.6.1.2.42 CH2_CFG3 Register (page = 0x00, address = 0x44) [reset = 80h]
            1. Table 86. CH2_CFG3 Register Field Descriptions
          43. 7.6.1.2.43 CH2_CFG4 Register (page = 0x00, address = 0x45) [reset = 0h]
            1. Table 87. CH2_CFG4 Register Field Descriptions
          44. 7.6.1.2.44 CH3_CFG0 Register (page = 0x00, address = 0x46) [reset = 0h]
            1. Table 88. CH3_CFG0 Register Field Descriptions
          45. 7.6.1.2.45 CH3_CFG2 Register (page = 0x00, address = 0x48) [reset = C9h]
            1. Table 89. CH3_CFG2 Register Field Descriptions
          46. 7.6.1.2.46 CH3_CFG3 Register (page = 0x00, address = 0x49) [reset = 80h]
            1. Table 90. CH3_CFG3 Register Field Descriptions
          47. 7.6.1.2.47 CH3_CFG4 Register (page = 0x00, address = 0x4A) [reset = 0h]
            1. Table 91. CH3_CFG4 Register Field Descriptions
          48. 7.6.1.2.48 CH4_CFG0 Register (page = 0x00, address = 0x4B) [reset = 0h]
            1. Table 92. CH4_CFG0 Register Field Descriptions
          49. 7.6.1.2.49 CH4_CFG2 Register (page = 0x00, address = 0x4D) [reset = C9h]
            1. Table 93. CH4_CFG2 Register Field Descriptions
          50. 7.6.1.2.50 CH4_CFG3 Register (page = 0x00, address = 0x4E) [reset = 80h]
            1. Table 94. CH4_CFG3 Register Field Descriptions
          51. 7.6.1.2.51 CH4_CFG4 Register (page = 0x00, address = 0x4F) [reset = 0h]
            1. Table 95. CH4_CFG4 Register Field Descriptions
          52. 7.6.1.2.52 CH5_CFG0 Register (page = 0x00, address = 0x50) [reset = 0h]
            1. Table 96. CH5_CFG0 Register Field Descriptions
          53. 7.6.1.2.53 CH5_CFG2 Register (page = 0x00, address = 0x52) [reset = C9h]
            1. Table 97. CH5_CFG2 Register Field Descriptions
          54. 7.6.1.2.54 CH5_CFG3 Register (page = 0x00, address = 0x53) [reset = 80h]
            1. Table 98. CH5_CFG3 Register Field Descriptions
          55. 7.6.1.2.55 CH5_CFG4 Register (page = 0x00, address = 0x54) [reset = 0h]
            1. Table 99. CH5_CFG4 Register Field Descriptions
          56. 7.6.1.2.56 CH6_CFG0 Register (page = 0x00, address = 0x55) [reset = 0h]
            1. Table 100. CH6_CFG0 Register Field Descriptions
          57. 7.6.1.2.57 CH6_CFG2 Register (page = 0x00, address = 0x57) [reset = C9h]
            1. Table 101. CH6_CFG2 Register Field Descriptions
          58. 7.6.1.2.58 CH6_CFG3 Register (page = 0x00, address = 0x58) [reset = 80h]
            1. Table 102. CH6_CFG3 Register Field Descriptions
          59. 7.6.1.2.59 CH6_CFG4 Register (page = 0x00, address = 0x59) [reset = 0h]
            1. Table 103. CH6_CFG4 Register Field Descriptions
          60. 7.6.1.2.60 CH7_CFG0 Register (page = 0x00, address = 0x5A) [reset = 0h]
            1. Table 104. CH7_CFG0 Register Field Descriptions
          61. 7.6.1.2.61 CH7_CFG2 Register (page = 0x00, address = 0x5C) [reset = C9h]
            1. Table 105. CH7_CFG2 Register Field Descriptions
          62. 7.6.1.2.62 CH7_CFG3 Register (page = 0x00, address = 0x5D) [reset = 80h]
            1. Table 106. CH7_CFG3 Register Field Descriptions
          63. 7.6.1.2.63 CH7_CFG4 Register (page = 0x00, address = 0x5E) [reset = 0h]
            1. Table 107. CH7_CFG4 Register Field Descriptions
          64. 7.6.1.2.64 CH8_CFG0 Register (page = 0x00, address = 0x5F) [reset = 0h]
            1. Table 108. CH8_CFG0 Register Field Descriptions
          65. 7.6.1.2.65 CH8_CFG2 Register (page = 0x00, address = 0x61) [reset = C9h]
            1. Table 109. CH8_CFG2 Register Field Descriptions
          66. 7.6.1.2.66 CH8_CFG3 Register (page = 0x00, address = 0x62) [reset = 80h]
            1. Table 110. CH8_CFG3 Register Field Descriptions
          67. 7.6.1.2.67 CH8_CFG4 Register (page = 0x00, address = 0x63) [reset = 0h]
            1. Table 111. CH8_CFG4 Register Field Descriptions
          68. 7.6.1.2.68 DSP_CFG0 Register (page = 0x00, address = 0x6B) [reset = 1h]
            1. Table 112. DSP_CFG0 Register Field Descriptions
          69. 7.6.1.2.69 DSP_CFG1 Register (page = 0x00, address = 0x6C) [reset = 40h]
            1. Table 113. DSP_CFG1 Register Field Descriptions
          70. 7.6.1.2.70 IN_CH_EN Register (page = 0x00, address = 0x73) [reset = F0h]
            1. Table 114. IN_CH_EN Register Field Descriptions
          71. 7.6.1.2.71 ASI_OUT_CH_EN Register (page = 0x00, address = 0x74) [reset = 0h]
            1. Table 115. ASI_OUT_CH_EN Register Field Descriptions
          72. 7.6.1.2.72 PWR_CFG Register (page = 0x00, address = 0x75) [reset = 0h]
            1. Table 116. PWR_CFG Register Field Descriptions
          73. 7.6.1.2.73 DEV_STS0 Register (page = 0x00, address = 0x76) [reset = 0h]
            1. Table 117. DEV_STS0 Register Field Descriptions
          74. 7.6.1.2.74 DEV_STS1 Register (page = 0x00, address = 0x77) [reset = 80h]
            1. Table 118. DEV_STS1 Register Field Descriptions
          75. 7.6.1.2.75 I2C_CKSUM Register (page = 0x00, address = 0x7E) [reset = 0h]
            1. Table 119. I2C_CKSUM Register Field Descriptions
      2. 7.6.2 Programmable Coefficient Registers
        1. 7.6.2.1 Programmable Coefficient Registers: Page = 0x02
        2. 7.6.2.2 Programmable Coefficient Registers: Page = 0x03
        3. 7.6.2.3 Programmable Coefficient Registers: Page = 0x04
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Eight-Channel Digital PDM Microphone Recording
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Example Device Register Configuration Script for EVM Setup
        3. 8.2.1.3 Application Curves
    3. 8.3 What to Do and What Not to Do
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

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7.3.1.2 Audio Serial Interfaces

Digital audio data flows between the host processor and the PCMD3180 on the digital audio serial interface (ASI), or audio bus. This highly flexible ASI bus includes a TDM mode for multichannel operation, support for I2S or left-justified protocols format, programmable data length options, very flexible master-slave configurability for bus clock lines and the ability to communicate with multiple devices within a system directly.

The bus protocol TDM, I2S, or left-justified (LJ) format can be selected by using the ASI_FORMAT[1:0], P0_R7_D[7:6] register bits. As shown in Table 2 and Table 3, these modes are all most significant byte (MSB)-first, pulse code modulation (PCM) data format, with the output channel data word-length programmable as 16, 20, 24, or 32 bits by configuring the ASI_WLEN[1:0], P0_R7_D[5:4] register bits.

Table 2. Audio Serial Interface Format

P0_R7_D[7:6] : ASI_FORMAT[1:0] AUDIO SERIAL INTERFACE FORMAT
00 (default) Time division multiplexing (TDM) mode
01 Inter IC sound (I2S) mode
10 Left-justified (LJ) mode
11 Reserved (do not use this setting)

Table 3. Audio Output Channel Data Word-Length

P0_R7_D[5:4] : ASI_WLEN[1:0] AUDIO OUTPUT CHANNEL DATA WORD-LENGTH
00 Output channel data word-length set to 16 bits
01 Output channel data word-length set to 20 bits
10 Output channel data word-length set to 24 bits
11 (default) Output channel data word-length set to 32 bits

The frame sync pin, FSYNC, is used in this audio bus protocol to define the beginning of a frame and has the same frequency as the output data sample rates. The bit clock pin, BCLK, is used to clock out the digital audio data across the serial bus. The number of bit-clock cycles in a frame must accommodate multiple device active output channels with the programmed data word length.

A frame consists of multiple time-division channel slots (up to 64) to allow all output channel audio data transmissions to complete on the audio bus by a device or multiple PCMD3180 devices sharing the same audio bus. The device supports up to eight output channels that can be configured to place their audio data on bus slot 0 to slot 63. Table 4 lists the output channel slot configuration settings. In I2S and LJ mode, the slots are divided into two sets, left-channel slots and right-channel slots, as described in the Inter IC Sound (I2S) Interface and Left-Justified (LJ) Interface sections.

Table 4. Output Channel Slot Assignment Settings

P0_R11_D[5:0] : CH1_SLOT[5:0] OUTPUT CHANNEL 1 SLOT ASSIGNMENT
00 0000 = 0d (default) Slot 0 for TDM or left slot 0 for I2S, LJ.
00 0001 = 1d Slot 1 for TDM or left slot 1 for I2S, LJ.
… …
01 1111 = 31d Slot 31 for TDM or left slot 31 for I2S, LJ.
10 0000 = 32d Slot 32 for TDM or right slot 0 for I2S, LJ.
… …
11 1110 = 62d Slot 62 for TDM or right slot 30 for I2S, LJ.
11 1111 = 63d Slot 63 for TDM or right slot 31 for I2S, LJ.

Similarly, the slot assignment setting for output channel 2 to channel 8 can be done using the CH2_SLOT (P0_R12) to CH8_SLOT (P0_R18) registers, respectively.

The slot word length is the same as the output channel data word length set for the device. The output channel data word length must be set to the same value for all PCMD3180 devices if all devices share the same ASI bus in a system. The maximum number of slots possible for the ASI bus in a system is limited by the available bus bandwidth, which depends upon the BCLK frequency, output data sample rate used, and the channel data word length configured.

The device also includes a feature that offsets the start of the slot data transfer with respect to the frame sync by up to 31 cycles of the bit clock. Table 5 lists the programmable offset configuration settings.

Table 5. Programmable Offset Settings for the ASI Slot Start

P0_R8_D[4:0] : TX_OFFSET[4:0] PROGRAMMABLE OFFSET SETTING FOR SLOT DATA TRANSMISSION START
0 0000 = 0d (default) The device follows the standard protocol timing without any offset.
0 0001 = 1d Slot start is offset by one BCLK cycle, as compared to standard protocol timing.
For I2S or LJ, the left and right slot start is offset by one BCLK cycle, as compared to standard protocol timing.
...... ......
1 1110 = 30d Slot start is offset by 30 BCLK cycles, as compared to standard protocol timing.
For I2S or LJ, the left and right slot start is offset by 30 BCLK cycles, as compared to standard protocol timing.
1 1111 = 31d Slot start is offset by 31 BCLK cycles, as compared to standard protocol timing.
For I2S or LJ, the left and right slot start is offset by 31 BCLK cycles, as compared to standard protocol timing.

The device also features the ability to invert the polarity of the frame sync pin, FSYNC, used to transfer the audio data as compared to the default FSYNC polarity used in standard protocol timing. This feature can be set using the FSYNC_POL, P0_R7_D3 register bit. Similarly, the device can invert the polarity of the bit clock pin, BCLK, which can be set using the BCLK_POL, P0_R7_D2 register bit.