SBASA14A May   2020  – January 2026 PCMD3180

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  Timing Requirements: I2C Interface
    7. 5.7  Timing Requirements: SPI
    8. 5.8  Timing Requirements: TDM, I2S or LJ Interface
    9. 5.9  Timing Requirements: PDM Digital Microphone Interface
    10. 5.10 Switching Characteristics: I2C Interface
    11. 5.11 Switching Characteristics: SPI
    12. 5.12 Switching Characteristics: TDM, I2S or LJ Interface
    13. 5.13 Switching Characteristics: PDM Digial Microphone Interface
    14. 5.14 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Serial Interfaces
        1. 6.3.1.1 Control Serial Interfaces
        2. 6.3.1.2 Audio Serial Interfaces
          1. 6.3.1.2.1 Time Division Multiplexed Audio (TDM) Interface
          2. 6.3.1.2.2 Inter IC Sound (I2S) Interface
          3. 6.3.1.2.3 Left-Justified (LJ) Interface
        3. 6.3.1.3 Using Multiple Devices With Shared Buses
      2. 6.3.2 Phase-Locked Loop (PLL) and Clock Generation
      3. 6.3.3 Reference Voltage
      4. 6.3.4 Microphone Bias
      5. 6.3.5 Digital PDM Microphone Record Channel
      6. 6.3.6 Signal-Chain Processing
        1. 6.3.6.1 Programmable Digital Volume Control
        2. 6.3.6.2 Programmable Channel Gain Calibration
        3. 6.3.6.3 Programmable Channel Phase Calibration
        4. 6.3.6.4 Programmable Digital High-Pass Filter
        5. 6.3.6.5 Programmable Digital Biquad Filters
        6. 6.3.6.6 Programmable Channel Summer and Digital Mixer
        7. 6.3.6.7 Configurable Digital Decimation Filters
          1. 6.3.6.7.1 Linear Phase Filters
            1. 6.3.6.7.1.1 Sampling Rate: 8kHz or 7.35kHz
            2. 6.3.6.7.1.2 Sampling Rate: 16kHz or 14.7kHz
            3. 6.3.6.7.1.3 Sampling Rate: 24kHz or 22.05kHz
            4. 6.3.6.7.1.4 Sampling Rate: 32kHz or 29.4kHz
            5. 6.3.6.7.1.5 Sampling Rate: 48kHz or 44.1kHz
            6. 6.3.6.7.1.6 Sampling Rate: 96kHz or 88.2kHz
            7. 6.3.6.7.1.7 Sampling Rate: 192kHz or 176.4kHz
            8. 6.3.6.7.1.8 Sampling Rate: 384kHz or 352.8kHz
            9. 6.3.6.7.1.9 Sampling Rate 768kHz or 705.6kHz
          2. 6.3.6.7.2 Low-Latency Filters
            1. 6.3.6.7.2.1 Sampling Rate: 16kHz or 14.7kHz
            2. 6.3.6.7.2.2 Sampling Rate: 24kHz or 22.05kHz
            3. 6.3.6.7.2.3 Sampling Rate: 32kHz or 29.4kHz
            4. 6.3.6.7.2.4 Sampling Rate: 48kHz or 44.1kHz
            5. 6.3.6.7.2.5 Sampling Rate: 96kHz or 88.2kHz
            6. 6.3.6.7.2.6 Sampling Rate 192kHz or 176.4kHz
          3. 6.3.6.7.3 Ultra-Low-Latency Filters
            1. 6.3.6.7.3.1 Sampling Rate: 16kHz or 14.7kHz
            2. 6.3.6.7.3.2 Sampling Rate: 24kHz or 22.05kHz
            3. 6.3.6.7.3.3 Sampling Rate: 32kHz or 29.4kHz
            4. 6.3.6.7.3.4 Sampling Rate: 48kHz or 44.1kHz
            5. 6.3.6.7.3.5 Sampling Rate: 96kHz or 88.2kHz
            6. 6.3.6.7.3.6 Sampling Rate 192kHz or 176.4kHz
            7. 6.3.6.7.3.7 Sampling Rate 384kHz or 352.8kHz
      7. 6.3.7 Interrupts, Status, and Digital I/O Pin Multiplexing
    4. 6.4 Device Functional Modes
      1. 6.4.1 Hardware Shutdown
      2. 6.4.2 Sleep Mode or Software Shutdown
      3. 6.4.3 Active Mode
      4. 6.4.4 Software Reset
    5. 6.5 Programming
      1. 6.5.1 Control Serial Interfaces
        1. 6.5.1.1 I2C Control Interface
          1. 6.5.1.1.1 General I2C Operation
          2. 6.5.1.1.2 I2C Single-Byte and Multiple-Byte Transfers
            1. 6.5.1.1.2.1 I2C Single-Byte Write
            2. 6.5.1.1.2.2 I2C Multiple-Byte Write
            3. 6.5.1.1.2.3 I2C Single-Byte Read
            4. 6.5.1.1.2.4 I2C Multiple-Byte Read
        2. 6.5.1.2 SPI Control Interface
  8. 7 Register Maps
    1. 7.1 Device Configuration Registers
      1. 7.1.1 Register Summary Table Page=0x00
      2. 7.1.2 Register Descriptions
        1. 7.1.2.1  PAGE_CFG Register (page = 0x00, address = 0x00) [reset = 0h]
        2. 7.1.2.2  SW_RESET Register (page = 0x00, address = 0x01) [reset = 0h]
        3. 7.1.2.3  SLEEP_CFG Register (page = 0x00, address = 0x02) [reset = 0h]
        4. 7.1.2.4  SHDN_CFG Register (page = 0x00, address = 0x05) [reset = 5h]
        5. 7.1.2.5  ASI_CFG0 Register (page = 0x00, address = 0x07) [reset = 30h]
        6. 7.1.2.6  ASI_CFG1 Register (page = 0x00, address = 0x08) [reset = 0h]
        7. 7.1.2.7  ASI_CFG2 Register (page = 0x00, address = 0x09) [reset = 0h]
        8. 7.1.2.8  ASI_CH1 Register (page = 0x00, address = 0x0B) [reset = 0h]
        9. 7.1.2.9  ASI_CH2 Register (page = 0x00, address = 0x0C) [reset = 1h]
        10. 7.1.2.10 ASI_CH3 Register (page = 0x00, address = 0x0D) [reset = 2h]
        11. 7.1.2.11 ASI_CH4 Register (page = 0x00, address = 0x0E) [reset = 3h]
        12. 7.1.2.12 ASI_CH5 Register (page = 0x00, address = 0x0F) [reset = 4h]
        13. 7.1.2.13 ASI_CH6 Register (page = 0x00, address = 0x10) [reset = 5h]
        14. 7.1.2.14 ASI_CH7 Register (page = 0x00, address = 0x11) [reset = 6h]
        15. 7.1.2.15 ASI_CH8 Register (page = 0x00, address = 0x12) [reset = 7h]
        16. 7.1.2.16 MST_CFG0 Register (page = 0x00, address = 0x13) [reset = 2h]
        17. 7.1.2.17 MST_CFG1 Register (page = 0x00, address = 0x14) [reset = 48h]
        18. 7.1.2.18 ASI_STS Register (page = 0x00, address = 0x15) [reset = FFh]
        19. 7.1.2.19 CLK_SRC Register (page = 0x00, address = 0x16) [reset = 10h]
        20. 7.1.2.20 PDMCLK_CFG Register (page = 0x00, address = 0x1F) [reset = 40h]
        21. 7.1.2.21 PDMIN_CFG Register (page = 0x00, address = 0x20) [reset = 0h]
        22. 7.1.2.22 GPIO_CFG0 Register (page = 0x00, address = 0x21) [reset = 22h]
        23. 7.1.2.23 GPO_CFG0 Register (page = 0x00, address = 0x22) [reset = 0h]
        24. 7.1.2.24 GPO_CFG1 Register (page = 0x00, address = 0x23) [reset = 0h]
        25. 7.1.2.25 GPO_CFG2 Register (page = 0x00, address = 0x24) [reset = 0h]
        26. 7.1.2.26 GPO_CFG3 Register (page = 0x00, address = 0x25) [reset = 0h]
        27. 7.1.2.27 GPO_VAL Register (page = 0x00, address = 0x29) [reset = 0h]
        28. 7.1.2.28 GPIO_MON Register (page = 0x00, address = 0x2A) [reset = 0h]
        29. 7.1.2.29 GPI_CFG0 Register (page = 0x00, address = 0x2B) [reset = 0h]
        30. 7.1.2.30 GPI_CFG1 Register (page = 0x00, address = 0x2C) [reset = 0h]
        31. 7.1.2.31 GPI_MON Register (page = 0x00, address = 0x2F) [reset = 0h]
        32. 7.1.2.32 INT_CFG Register (page = 0x00, address = 0x32) [reset = 0h]
        33. 7.1.2.33 INT_MASK0 Register (page = 0x00, address = 0x33) [reset = FFh]
        34. 7.1.2.34 INT_LTCH0 Register (page = 0x00, address = 0x36) [reset = 0h]
        35. 7.1.2.35 BIAS_CFG Register (page = 0x00, address = 0x3B) [reset = 0h]
        36. 7.1.2.36 CH1_CFG0 Register (page = 0x00, address = 0x3C) [reset = 0h]
        37. 7.1.2.37 CH1_CFG2 Register (page = 0x00, address = 0x3E) [reset = C9h]
        38. 7.1.2.38 CH1_CFG3 Register (page = 0x00, address = 0x3F) [reset = 80h]
        39. 7.1.2.39 CH1_CFG4 Register (page = 0x00, address = 0x40) [reset = 0h]
        40. 7.1.2.40 CH2_CFG0 Register (page = 0x00, address = 0x41) [reset = 0h]
        41. 7.1.2.41 CH2_CFG2 Register (page = 0x00, address = 0x43) [reset = C9h]
        42. 7.1.2.42 CH2_CFG3 Register (page = 0x00, address = 0x44) [reset = 80h]
        43. 7.1.2.43 CH2_CFG4 Register (page = 0x00, address = 0x45) [reset = 0h]
        44. 7.1.2.44 CH3_CFG0 Register (page = 0x00, address = 0x46) [reset = 0h]
        45. 7.1.2.45 CH3_CFG2 Register (page = 0x00, address = 0x48) [reset = C9h]
        46. 7.1.2.46 CH3_CFG3 Register (page = 0x00, address = 0x49) [reset = 80h]
        47. 7.1.2.47 CH3_CFG4 Register (page = 0x00, address = 0x4A) [reset = 0h]
        48. 7.1.2.48 CH4_CFG0 Register (page = 0x00, address = 0x4B) [reset = 0h]
        49. 7.1.2.49 CH4_CFG2 Register (page = 0x00, address = 0x4D) [reset = C9h]
        50. 7.1.2.50 CH4_CFG3 Register (page = 0x00, address = 0x4E) [reset = 80h]
        51. 7.1.2.51 CH4_CFG4 Register (page = 0x00, address = 0x4F) [reset = 0h]
        52. 7.1.2.52 CH5_CFG0 Register (page = 0x00, address = 0x50) [reset = 0h]
        53. 7.1.2.53 CH5_CFG2 Register (page = 0x00, address = 0x52) [reset = C9h]
        54. 7.1.2.54 CH5_CFG3 Register (page = 0x00, address = 0x53) [reset = 80h]
        55. 7.1.2.55 CH5_CFG4 Register (page = 0x00, address = 0x54) [reset = 0h]
        56. 7.1.2.56 CH6_CFG0 Register (page = 0x00, address = 0x55) [reset = 0h]
        57. 7.1.2.57 CH6_CFG2 Register (page = 0x00, address = 0x57) [reset = C9h]
        58. 7.1.2.58 CH6_CFG3 Register (page = 0x00, address = 0x58) [reset = 80h]
        59. 7.1.2.59 CH6_CFG4 Register (page = 0x00, address = 0x59) [reset = 0h]
        60. 7.1.2.60 CH7_CFG0 Register (page = 0x00, address = 0x5A) [reset = 0h]
        61. 7.1.2.61 CH7_CFG2 Register (page = 0x00, address = 0x5C) [reset = C9h]
        62. 7.1.2.62 CH7_CFG3 Register (page = 0x00, address = 0x5D) [reset = 80h]
        63. 7.1.2.63 CH7_CFG4 Register (page = 0x00, address = 0x5E) [reset = 0h]
        64. 7.1.2.64 CH8_CFG0 Register (page = 0x00, address = 0x5F) [reset = 0h]
        65. 7.1.2.65 CH8_CFG2 Register (page = 0x00, address = 0x61) [reset = C9h]
        66. 7.1.2.66 CH8_CFG3 Register (page = 0x00, address = 0x62) [reset = 80h]
        67. 7.1.2.67 CH8_CFG4 Register (page = 0x00, address = 0x63) [reset = 0h]
        68. 7.1.2.68 DSP_CFG0 Register (page = 0x00, address = 0x6B) [reset = 1h]
        69. 7.1.2.69 DSP_CFG1 Register (page = 0x00, address = 0x6C) [reset = 40h]
        70. 7.1.2.70 IN_CH_EN Register (page = 0x00, address = 0x73) [reset = F0h]
        71. 7.1.2.71 ASI_OUT_CH_EN Register (page = 0x00, address = 0x74) [reset = 0h]
        72. 7.1.2.72 PWR_CFG Register (page = 0x00, address = 0x75) [reset = 0h]
        73. 7.1.2.73 DEV_STS0 Register (page = 0x00, address = 0x76) [reset = 0h]
        74. 7.1.2.74 DEV_STS1 Register (page = 0x00, address = 0x77) [reset = 80h]
        75. 7.1.2.75 I2C_CKSUM Register (page = 0x00, address = 0x7E) [reset = 0h]
    2. 7.2 Programmable Coefficient Registers
      1. 7.2.1 Programmable Coefficient Registers: Page = 0x02
      2. 7.2.2 Programmable Coefficient Registers: Page = 0x03
      3. 7.2.3 Programmable Coefficient Registers: Page = 0x04
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Eight-Channel Digital PDM Microphone Recording
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Example Device Register Configuration Script for EVM Setup
        3. 8.2.1.3 Application Curves
    3. 8.3 What to Do and What Not to Do
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

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7.1.2.20 PDMCLK_CFG Register (page = 0x00, address = 0x1F) [reset = 40h]

This register is the PDM clock generation configuration register.

Figure 7-20 PDMCLK_CFG Register
76543210
ReservedReservedPDMCLK_DIV[1:0]
R/W-0hR/W-10hR/W-0h
Table 7-21 PDMCLK_CFG Register Field Descriptions
BitFieldTypeResetDescription
7ReservedR/W0hReserved
6-2ReservedR/W10hReserved
1-0PDMCLK_DIV[1:0]R/W0hPDMCLK divider value.
0d = PDMCLK is 2.8224MHz or 3.072MHz
1d = PDMCLK is 1.4112MHz or 1.536MHz
2d = PDMCLK is 705.6kHz or 768kHz
3d = PDMCLK is 5.6448MHz or 6.144MHz