ZHCSAC2C August   2012  – October 2018 PCM5121 , PCM5122

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      简化系统图
  4. 4 修订历史记录
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
    1. 6.0.1 RHB Package I2C Mode (MODE1 tied to DGND and MODE2 tied to DVDD) Top View
    2. 6.0.2 RHB Package SPI Mode (MODE1 tied to DVDD) Top View
    3. 6.0.3 RHB Package Hardwired Mode (MODE1 tied to DGND, MODE2 tied to DGND) Top View
    4.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements: SCK Input
    7. 7.7 Timing Requirements: XSMT
    8. 7.8 Switching Characteristics
    9. 7.9 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Terminology
      2. 8.3.2 Audio Data Interface
        1. 8.3.2.1 Audio Serial Interface
        2. 8.3.2.2 PCM Audio Data Formats
        3. 8.3.2.3 Zero Data Detect
      3. 8.3.3 XSMT Pin (Soft Mute / Soft Un-Mute)
      4. 8.3.4 Audio Processing
        1. 8.3.4.1 PCM512x Audio Processing
          1. 8.3.4.1.1 Overview
          2. 8.3.4.1.2 Software
        2. 8.3.4.2 Interpolation Filter
        3. 8.3.4.3 Fixed Audio Processing Flow (Program 5)
          1. 8.3.4.3.1 Filter Programming Changes
          2. 8.3.4.3.2 Processing Blocks – Detailed Descriptions
          3. 8.3.4.3.3 Biquad Section
          4. 8.3.4.3.4 Dynamic Range Compression
          5. 8.3.4.3.5 Stereo Mixer
          6. 8.3.4.3.6 Stereo Multiplexer
          7. 8.3.4.3.7 Mono Mixer
          8. 8.3.4.3.8 Master Volume Control
          9. 8.3.4.3.9 Miscellaneous Coefficients
      5. 8.3.5 DAC Outputs
        1. 8.3.5.1 Analog Outputs
        2. 8.3.5.2 Recommended Output Filter for the PCM512x
        3. 8.3.5.3 Choosing Between VREF and VCOM Modes
          1. 8.3.5.3.1 Voltage Reference and Output Levels
          2. 8.3.5.3.2 Mode Switching Sequence, from VREF Mode to VCOM Mode
        4. 8.3.5.4 Digital Volume Control
          1. 8.3.5.4.1 Emergency Ramp-Down
        5. 8.3.5.5 Analog Gain Control
      6. 8.3.6 Reset and System Clock Functions
        1. 8.3.6.1 Clocking Overview
        2. 8.3.6.2 Clock Slave Mode With Master and System Clock (SCK) Input (4 Wire I2S)
        3. 8.3.6.3 Clock Slave Mode With BCK PLL to Generate Internal Clocks (3-Wire PCM)
        4. 8.3.6.4 Clock Generation Using the PLL
        5. 8.3.6.5 PLL Calculation
          1. 8.3.6.5.1 Examples:
            1. 8.3.6.5.1.1 Recommended PLL Settings
        6. 8.3.6.6 Clock Master Mode from Audio Rate Master Clock
        7. 8.3.6.7 Clock Master from a Non-Audio Rate Master Clock
    4. 8.4 Device Functional Modes
      1. 8.4.1 Choosing a Control Mode
        1. 8.4.1.1 Software Control
          1. 8.4.1.1.1 SPI Interface
            1. 8.4.1.1.1.1 Register Read and Write Operation
          2. 8.4.1.1.2 I2C Interface
            1. 8.4.1.1.2.1 Slave Address
            2. 8.4.1.1.2.2 Register Address Auto-Increment Mode
            3. 8.4.1.1.2.3 Packet Protocol
            4. 8.4.1.1.2.4 Write Register
            5. 8.4.1.1.2.5 Read Register
            6. 8.4.1.1.2.6 Timing Characteristics
      2. 8.4.2 VREF and VCOM Modes
    5. 8.5 Programming
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
    1. 10.1 Power Supply Distribution and Requirements
    2. 10.2 Recommended Powerdown Sequence
      1. 10.2.1 XSMT = 0
      2. 10.2.2 Clock Error Detect
      3. 10.2.3 Planned Shutdown
      4. 10.2.4 Unplanned Shutdown
    3. 10.3 External Power Sense Undervoltage Protection Mode
    4. 10.4 Power-On Reset Function
      1. 10.4.1 Power-On Reset, DVDD 3.3-V Supply
      2. 10.4.2 Power-On Reset, DVDD 1.8-V Supply
    5. 10.5 PCM512x Power Modes
      1. 10.5.1 Setting Digital Power Supplies and I/O Voltage Rails
      2. 10.5.2 Power Save Modes
      3. 10.5.3 Power Save Parameter Programming
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Register Maps
    1. 12.1 PCM512x Register Map
      1. 12.1.1 Detailed Register Descriptions
        1. 12.1.1.1 Register Map Summary
        2. 12.1.1.2 Page 0 Registers
        3. 12.1.1.3 Page 1 Registers
        4. 12.1.1.4 Page 44 Registers
        5. 12.1.1.5 Page 253 Registers
      2. 12.1.2 PLL Tables for Software Controlled Devices
      3. 12.1.3 Coefficient Data Formats
      4. 12.1.4 Power Down and Reset Behavior
  13. 13器件和文档支持
    1. 13.1 开发支持
    2. 13.2 文档支持
    3. 13.3 相关链接
    4. 13.4 接收文档更新通知
    5. 13.5 社区资源
    6. 13.6 商标
    7. 13.7 静电放电警告
    8. 13.8 术语表
  14. 14机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

8.3.4.3.4 Dynamic Range Compression

Dynamic range compression (DRC) improves the overall listening experience. Typical music signals are characterized by crest factors (the ratio of peak signal power to average signal power) of 12 dB or more. To avoid audible distortion due to clipping of peak signals, the gain of the DAC channel must be adjusted so as not to cause hard clipping. As a result, the low applied gain during nominal periods causes the perception that the signal is not loud enough. To overcome this problem, the DRC in the PCM512x continuously monitors the output of the DAC Digital Volume control to detect its power level with respect to 0-dB full-scale. When the power level is low, the DRC increases the input signal gain to make it sound louder, and reduces the gain during peaks to avoid hard clipping. The DRC enables louder audio during nominal periods with a clearer, more pleasant listening experience.

The 3-band DRC function applies DRC to 3 different mono/stereo signals with 3 different time constants. The same DRC curve is applied on all the signals, enabling a multi-band DRC solution. The underlying DRC algorithm is the same as that available with the DRC component in PurePath Studio. In this instance, the DRC gain acts on each signal in time-multiplexed order, for example, 1-2-3, 1-2-3, 1-2-3.

Table 22. DRC Coefficients

COEFFICIENT REGISTER
DRC_MB_1_DRC_1_DRCAE C70 (Pg 46, Reg 48, 49, 50, 51)
DRC_MB_1_DRC_1_DRC1AE C71 (Pg 46, Reg 52, 53, 54, 55)
DRC_MB_1_DRC_1_DRCAA C72 (Pg 46, Reg 56, 57, 58, 59)
DRC_MB_1_DRC_1_DRC1AA C73 (Pg 46, Reg 60, 61, 62, 63)
DRC_MB_1_DRC_1_DRCAD C74 (Pg 46, Reg 64, 65, 66, 67)
DRC_MB_1_DRC_1_DRC1AD C75 (Pg 46, Reg 68, 69, 70, 71)
DRC_MB_1_DRC_2_DRCAE C76 (Pg 46, Reg 72, 73, 74, 75)
DRC_MB_1_DRC_2_DRC1AE C77 (Pg 46, Reg 76, 77, 78, 79)
DRC_MB_1_DRC_2_DRCAA C78 (Pg 46, Reg 80, 81, 82, 83)
DRC_MB_1_DRC_2_DRC1AA C79 (Pg 46, Reg 84, 85, 86, 87)
DRC_MB_1_DRC_2_DRCAD C80 (Pg 46, Reg 88, 89, 90, 91)
DRC_MB_1_DRC_2_DRC1AD C81 (Pg 46, Reg 92, 93, 94, 95)
DRC_MB_1_DRC_3_DRCAE C82 (Pg 46, Reg 96, 97, 98, 99)
DRC_MB_1_DRC_3_DRC1AE C83 (Pg 46, Reg 100, 101, 102, 103)
DRC_MB_1_DRC_3_DRCAA C84 (Pg 46, Reg 104, 105, 106, 107)
DRC_MB_1_DRC_3_DRC1AA C85 (Pg 46, Reg 108, 109, 119, 111)
DRC_MB_1_DRC_3_DRCAD C86 (Pg 46, Reg 112, 113, 114, 115)
DRC_MB_1_DRC_3_DRC1AD C87 (Pg 46, Reg 116, 117, 118, 119)
DRC_MB_1_DRC_DRCK0 C88 (Pg 46, Reg 120, 121, 122, 123)
DRC_MB_1_DRC_DRCK1 C89 (Pg 46, Reg 124, 125, 126, 127)
DRC_MB_1_DRC_DRCK2 C90 (Pg 47, Reg 8, 9, 10, 11)
DRC_MB_1_DRC_DRCMT1 C91 (Pg 47, Reg 12, 13, 14, 15)
DRC_MB_1_DRC_DRCMT2 C92 (Pg 47, Reg 16, 17, 18, 19)
DRC_MB_1_DRC_DRCOFF1 C93 (Pg 47, Reg 20, 21, 22, 23)
DRC_MB_1_DRC_DRCOFF2 C94 (Pg 47, Reg 24, 25, 26, 27)
DRC_MB_1_MinusOne_Q22 C95 (Pg 47, Reg 28, 29, 30, 31)
DRC_MB_1_MinusTwo_Q22 C96 (Pg 47, Reg 32, 33, 34, 35)
DRC_MB_1_One_M2 C97 (Pg 47, Reg 36, 37, 38, 39)
DRC_MB_1_Zero C98 (Pg 47, Reg 40, 41, 42, 43)
DRC_MB_1_En_dB C99 (Pg 47, Reg 44, 45, 46, 47)
DRC_MB_1_Minus__Zero_dB C100 (Pg 47, Reg 48, 49, 50, 51)
DRC_MB_1_60_dB C101 (Pg 47, Reg 52, 53, 54, 55)
DRC_MB_1_Minus_60_dB C102 (Pg 47, Reg 56, 57, 58, 59)
DRC_MB_1_12_dB C103 (Pg 47, Reg 60, 61, 62, 63)
DRC_MB_1_Offset C104 (Pg 47, Reg 64, 65, 66, 67)
DRC_MB_1_K C105 (Pg 47, Reg 68, 69, 70, 71)
DRC_MB_1_x / DRC_MB_1_DRC C106 (Pg 47, Reg 72, 73, 74, 75)
DRC_MB_1_48_dB C107 (Pg 47, Reg 76, 77, 78, 79)
DRC_MB_1_Minus_48_dB C108 (Pg 47, Reg 80, 81, 82, 83)
DRC_MB_1_c1_3 C109 (Pg 47, Reg 84, 85, 86, 87)
DRC_MB_1_c1_2 C110 (Pg 47, Reg 88, 89, 90, 91)
DRC_MB_1_c1_1 C111 (Pg 47, Reg 92, 93, 94, 95)
DRC_MB_1_c1_0 C112 (Pg 47, Reg 96, 97, 98, 99)
DRC_MB_1_O1_1 C113 (Pg 47, Reg 100, 101, 102, 103)
DRC_MB_1_S1_1 C114 (Pg 47, Reg 104, 105, 106, 107)
DRC_MB_1_O1_2 C115 (Pg 47, Reg 108, 109, 119, 111)
DRC_MB_1_S1_2 C116 (Pg 47, Reg 112, 113, 114, 115)
DRC_MB_1_O1_3 C117 (Pg 47, Reg 116, 117, 118, 119)
DRC_MB_1_S1_3 C118 (Pg 47, Reg 120, 121, 122, 123)
DRC_MB_1_One_1_Q17 C119 (Pg 47, Reg 124, 125, 126, 127)
DRC_MB_1_Scale1 C120 (Pg 48, Reg 8, 9, 10, 11)
DRC_MB_1_x1Coeff C121 (Pg 48, Reg 12, 13, 14, 15)
DRC_MB_1_c2_3 C122 (Pg 48, Reg 16, 17, 18, 19)
DRC_MB_1_c2_2 C123 (Pg 48, Reg 20, 21, 22, 23)
DRC_MB_1_c2_1 C124 (Pg 48, Reg 24, 25, 26, 27)
DRC_MB_1_c2_0 C125 (Pg 48, Reg 28, 29, 30, 31)
DRC_MB_1_O2_1 C126 (Pg 48, Reg 32, 33, 34, 35)
DRC_MB_1_S2_1 C127 (Pg 48, Reg 36, 37, 38, 39)
DRC_MB_1_O2_2 C128 (Pg 48, Reg 40, 41, 42, 43)
DRC_MB_1_S2_2 C129 (Pg 48, Reg 44, 45, 46, 47)
DRC_MB_1_O2_3 C130 (Pg 48, Reg 48, 49, 50, 51)
DRC_MB_1_S2_3 C131 (Pg 48, Reg 52, 53, 54, 55)
DRC_MB_1_One_2_Q17 C132 (Pg 48, Reg 56, 57, 58, 59)
DRC_MB_1_Scale2 C133 (Pg 48, Reg 60, 61, 62, 63)
DRC_MB_1_x2Coeff C134 (Pg 48, Reg 64, 65, 66, 67)
DRC_MB_1_R1_1 C135 (Pg 48, Reg 68, 69, 70, 71)
DRC_MB_1_R1_2 C136 (Pg 48, Reg 72, 73, 74, 75)
DRC_MB_1_R2_1 C137 (Pg 48, Reg 76, 77, 78, 79)
DRC_MB_1_R2_2 C138 (Pg 48, Reg 80, 81, 82, 83)
DRC_MB_1_Band1_GainC C139 (Pg 48, Reg 84, 85, 86, 87)
DRC_MB_1_Band2_GainC C140 (Pg 48, Reg 88, 89, 90, 91)
DRC_MB_1_Band3_GainC C141 (Pg 48, Reg 92, 93, 94, 95)
DRC_MB_1_MinusOne_M1 C142 (Pg 48, Reg 96, 97, 98, 99)
DRC_MB_1_One_M1 C143 (Pg 48, Reg 100, 101, 102, 103)
DRC_MB_1_Band1_GainE C144 (Pg 48, Reg 104, 105, 106, 107)
DRC_MB_1_Band2_GainE C145 (Pg 48, Reg 108, 109, 110, 111)
DRC_MB_1_Band3_GainE C146 (Pg 48, Reg 112, 113, 114, 115)
DRC_MB_1_minus_One_M2 C147 (Pg 48, Reg 116, 117, 118, 119)