SBAS452A September   2008  – January 2016 PCM3168A

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Description (continued)
  6. Device Comparison Table
  7. Pin Configuration and Functions
  8. Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Thermal Information
    5. 8.5  Electrical Characteristics
    6. 8.6  Timing Requirements: System Clock
    7. 8.7  Timing Requirements: Power-On Reset
    8. 8.8  Timing Requirements: Audio Interface for Left-Justified, Right-Justified, and I2S (Slave Mode)
    9. 8.9  Timing Requirements: Audio Interface for Left-Justified, Right-Justified, and I2S (Master Mode)
    10. 8.10 Timing Requirements: Audio Interface for DSP and TDM (Slave Mode)
    11. 8.11 Timing Requirements: Audio Interface for DSP and TDM (Master Mode)
    12. 8.12 Timing Requirements: DAC Outputs and ADC Outputs
    13. 8.13 Timing Requirements: Four-Wire Serial Control Interface
    14. 8.14 Timing Requirements: SCL and SDA Control Interface
    15. 8.15 Typical Characteristics
      1. 8.15.1 ADC Digital Filter
      2. 8.15.2 DAC Digital Filter
      3. 8.15.3 ADC Performance
      4. 8.15.4 DAC Performance
      5. 8.15.5 Output Spectrum
      6. 8.15.6 Power-Supply
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Analog Inputs
      2. 9.3.2  Analog Outputs
      3. 9.3.3  Voltage References
      4. 9.3.4  System Clock Input
      5. 9.3.5  Sampling Mode
      6. 9.3.6  Reset Operation
      7. 9.3.7  Highpass Filter (HPF)
      8. 9.3.8  Overflow Flag
      9. 9.3.9  Zero Flag
      10. 9.3.10 Four-Wire (SPI) Serial Control
      11. 9.3.11 Control Data Word Format
      12. 9.3.12 Register Write Operation
      13. 9.3.13 Register Read Operation
      14. 9.3.14 Two-Wire (I2C) Serial Control
      15. 9.3.15 Packet Protocol
      16. 9.3.16 Write Operation
      17. 9.3.17 Read Operation
    4. 9.4 Device Functional Modes
      1. 9.4.1 Mode Control
      2. 9.4.2 Hardware Control Mode Configuration
      3. 9.4.3 Audio Serial Port Operation
      4. 9.4.4 Audio Data Interface Formats and Timing
      5. 9.4.5 Synchronization With the Digital Audio System
    5. 9.5 Register Maps
      1. 9.5.1 Control Register Definitions (Software Mode Only)
      2. 9.5.2 Register Definitions
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Analog Input and Output
        2. 10.2.2.2 PCM Interface
      3. 10.2.3 Application Curves
    3. 10.3 System Examples
      1. 10.3.1 Typical Circuit Connections
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1  Power-Supply Pins (VCCAD1/2, VCCDA1/2, and VDD1/2)
      2. 12.1.2  Grounding (AGNDAD1/2, AGNDDA1/2, and DGND1/2)
      3. 12.1.3  VIN1±, VIN2±, VIN3±, VIN4±, VIN5±, and VIN6± Pins
      4. 12.1.4  VCOMAD and VCOMDA Pins
      5. 12.1.5  VREFAD1/2 Pins
      6. 12.1.6  VOUT1±, VOU2±, VOUT3±, VOUT4±, VOUT5±, VOUT6±, VOUT7±, and VOUT8± Pins
      7. 12.1.7  MODE Pin
      8. 12.1.8  RST Pin
      9. 12.1.9  OVF Pin
      10. 12.1.10 System Clock and Audio Interface Clocks
      11. 12.1.11 PowerPAD
      12. 12.1.12 External Mute Control
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Third-Party Products Disclaimer
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 Community Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

12 Layout

12.1 Layout Guidelines

12.1.1 Power-Supply Pins (VCCAD1/2, VCCDA1/2, and VDD1/2)

The digital and analog power-supply pins of the PCM3168A device should be bypassed to the corresponding ground pins with 1-μF ceramic capacitors placed as close to the pins as possible. Each power-supply line (VCC and VDD) to the PCM3168A device should be bypassed to the corresponding ground pins with 10-μF electrolytic capacitors to maximize the dynamic performance of the ADC and DAC.

Although the PCM3168A device has two power lines to maximize the potential of dynamic performance, using one common source (for instance, a 5-V power supply for VCC and a 3.3-V power supply for VDD generated from one common source) is recommended to avoid unexpected power-supply trouble such as latch-up or incorrect power-supply conditions. Also, simultaneous power-on/off of VCC and VDD is recommended to avoid unexpected transient responses in outputs, though the power-supply sequence of VCC and VDD is not specified in the operation and absolute maximum ratings point of view.

12.1.2 Grounding (AGNDAD1/2, AGNDDA1/2, and DGND1/2)

To maximize the dynamic performance of the PCM3168A device, the analog and digital grounds are not connected internally. These pins should have very low impedances to avoid digital noise and signal components feeding back into the analog ground. All ground pins should be connected directly to each other under the part, and the device should be connected to the analog ground of the application, as with acceptable analog layout practices; this layout reduces the potential of noise problems.

12.1.3 VIN1±, VIN2±, VIN3±, VIN4±, VIN5±, and VIN6± Pins

In case of direct interface to VINx±, 1-μF electrolytic capacitors are recommended because the ac-coupling capacitor (which gives a 2-Hz HPF corner frequency and 47-Ω and 0.1-μF to 470-Ω and 0.001-μF differential LPF) is recommended as the anti-aliasing filter that gives a 160-kHz LPF corner frequency. If signal source impedance is not enough (too low) or input line length to the VINx± is not enough (too short), insertion of an analog front-end buffer (see Figure 58 to Figure 60) is recommended to maximize the dynamic performance. The voltage coefficient of the capacitor for an anti-aliasing filter should be considered to maximize the THD performance. A film-type capacitor is recommended; if a ceramic capacitor is used, a relatively higher voltage type is recommended.

There are three ways to terminate any unused input pins. First, terminate these pins to AGNDAD with 0.001-μF to 1-μF capacitors. This termination is applied on unused pins whose channels are configured in single-ended mode. The second form of termination is to connect the positive (+) pin and negative (–) pins together and terminating these to AGNDAD with 0.001-μF to 1-μF capacitors. This option applies to unused pins with channels that are configured in differential mode. The last termination method is to terminate the pins directly to VCOMAD; this option can be applied on unused pins with unused channels combined into two channels that are then configured in power-save mode.

12.1.4 VCOMAD and VCOMDA Pins

10-μF electrolytic capacitors are recommended between VCOMAD and AGNDAD, and VCOMDA and AGNDDA to ensure a low source impedance of ADC and DAC common voltages. These capacitors should be located as close to each pin as possible to reduce dynamic errors on the ADC and DAC common voltages.

12.1.5 VREFAD1/2 Pins

10-μF electrolytic capacitors are recommended between VREFAD1/2 and AGNDAD to ensure low source impedances of ADC references. These capacitors should be located as close to each pin as possible to reduce dynamic errors on ADC references.

12.1.6 VOUT1±, VOU2±, VOUT3±, VOUT4±, VOUT5±, VOUT6±, VOUT7±, and VOUT8± Pins

The differential to single-ended buffer with post LPF can be directly connected (without capacitors) to these output pins (see Figure 62), thereby minimizing the use of coupling capacitors for the 2-VRMS outputs. The op amp and resistors must be determined with consideration of degrading some performance through this differential to single-ended and LPF buffer; there is about 1.5-dB degradation seen in the examples of Figure 61 and Figure 62.

12.1.7 MODE Pin

This pin is a logic input with quad-state input capability. The MODE pin is high when connected to VDD, low when connected to DGND, and pulled up or pulled down through an external resistor and for the two mid-states in order to distinguish the four input states. The pull-up or pull-down resistor must be 220 kΩ, ±5% in tolerance. Note that the state of the MODE pin is only sampled by a power-on or a low-to-high transition of the RST pin.

12.1.8 RST Pin

When the MODE pin setting changes to change the operating mode, the new mode setting does not take effect immediately; a RST pin toggle is required to make the new mode setting valid, and for the new mode to take effect.

12.1.9 OVF Pin

The OVF pin has two functions. It is primarily the flag for ADC overflow occurrence detection. It is also used to indicate that the internal reset sequence is complete and that the device is ready to enter serial mode control.

12.1.10 System Clock and Audio Interface Clocks

The quality of SCKI may influence dynamic performance, because the PCM3168A device (both the ADC and DAC) operates based on SCKI. Therefore, it may be required to consider the jitter, duty, and rise and fall time of the system clock.

In slave mode, the PCM3168A device does not require a specific timing relationship between BCKAD/LRCKAD and SCKI, and BCKDA/LRCKDA and SCKI; however, there is a possibility of performance degradation with a certain timing relationship between them. In that case, specific timing relationship control might resolve this performance degradation.

In master mode, there is a possibility of performance degradation because of heavy loads on BCKAD/LRCKAD, BCKDA/LRCKDA, and DOUT1/2/3. It is recommended to load these pins as lightly as possible. Note that all output clocks and signals go low; they do not go into a high-impedance state during power-save mode.

12.1.11 PowerPAD

The PowerPAD of the PCM3168A device is internally connected to the substrate of the silicon. It should be connected to the ground plane with sufficient low conductance in electrical and thermal; see Figure 54. The PowerPAD size is 7.25 mm x 7.00 mm (0.725 cm × 0.7 cm).

12.1.12 External Mute Control

For power-down ON/OFF control without the pop-noise that is generated by a DC level change on the DAC output, the external mute control is generally required. Use of the following control sequence is recommended: external mute ON, codec power-down ON, SCKI stop and resume if necessary, codec power-down OFF, and external mute OFF control.

12.2 Layout Example

PCM3168A layout_ex_sbas452.gif Figure 64. PCM3168A Board Layout