ZHCSQ26 May   2022 PCM1822

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements: TDM or I2S Interface
    7. 7.7 Switching Characteristics: TDM or I2S Interface
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Hardware Control
      2. 8.3.2 Audio Serial Interfaces
        1. 8.3.2.1 Time Division Multiplexed Audio (TDM) Interface
        2. 8.3.2.2 Inter IC Sound (I2S) Interface
      3. 8.3.3 Phase-Locked Loop (PLL) and Clock Generation
      4. 8.3.4 Input Channel Configurations
      5. 8.3.5 Reference Voltage
      6. 8.3.6 Signal-Chain Processing
        1. 8.3.6.1 Digital High-Pass Filter
        2. 8.3.6.2 Configurable Digital Decimation Filters
          1. 8.3.6.2.1 Linear Phase Filters
            1. 8.3.6.2.1.1 Sampling Rate: 8 kHz or 7.35 kHz
            2. 8.3.6.2.1.2 Sampling Rate: 16 kHz or 14.7 kHz
            3. 8.3.6.2.1.3 Sampling Rate: 24 kHz or 22.05 kHz
            4. 8.3.6.2.1.4 Sampling Rate: 32 kHz or 29.4 kHz
            5. 8.3.6.2.1.5 Sampling Rate: 48 kHz or 44.1 kHz
            6. 8.3.6.2.1.6 Sampling Rate: 96 kHz or 88.2 kHz
            7. 8.3.6.2.1.7 Sampling Rate: 192 kHz or 176.4 kHz
          2. 8.3.6.2.2 Low-Latency Filters
            1. 8.3.6.2.2.1 Sampling Rate: 16 kHz or 14.7 kHz
            2. 8.3.6.2.2.2 Sampling Rate: 24 kHz or 22.05 kHz
            3. 8.3.6.2.2.3 Sampling Rate: 32 kHz or 29.4 kHz
            4. 8.3.6.2.2.4 Sampling Rate: 48 kHz or 44.1 kHz
            5. 8.3.6.2.2.5 Sampling Rate: 96 kHz or 88.2 kHz
      7. 8.3.7 Dynamic Range Enhancer (DRE)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Active Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 接收文档更新通知
    2. 12.2 支持资源
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 术语表
  13. 13Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

8.3.3 Phase-Locked Loop (PLL) and Clock Generation

The device uses an integrated, low-jitter, phase-locked loop (PLL) to generate internal clocks required for the ADC modulator and digital filter engine, as well as other control blocks.

In slave mode of operation, the device supports the various output data sample rates (of the FSYNC signal frequency) and the BCLK to FSYNC ratio to configure all clock dividers, including the PLL configuration, internally without host programming. Table 8-3 and Table 8-4 list the supported FSYNC and BCLK frequencies.

Table 8-3 Supported FSYNC (Multiples or Submultiples of 48 kHz) and BCLK Frequencies
BCLK TO FSYNC RATIOBCLK (MHz)
FSYNC
(8 kHz)		FSYNC
(16 kHz)		FSYNC
(24 kHz)		FSYNC
(32 kHz)		FSYNC
(48 kHz)		FSYNC
(96 kHz)		FSYNC
(192 kHz)
16Reserved0.2560.3840.5120.7681.5363.072
24Reserved0.3840.5760.7681.1522.3044.608
320.2560.5120.7681.0241.5363.0726.144
480.3840.7681.1521.5362.3044.6089.216
640.5121.0241.5362.0483.0726.14412.288
960.7681.5362.3043.0724.6089.21618.432
1281.0242.0483.0724.0966.14412.28824.576
1921.5363.0724.6086.1449.21618.432Reserved
2562.0484.0966.1448.19212.28824.576Reserved
3843.0726.1449.21612.28818.432ReservedReserved
5124.0968.19212.28816.38424.576ReservedReserved
Table 8-4 Supported FSYNC (Multiples or Submultiples of 44.1 kHz) and BCLK Frequencies
BCLK TO FSYNC RATIOBCLK (MHz)
FSYNC
(7.35 kHz)		FSYNC
(14.7 kHz)		FSYNC
(22.05 kHz)		FSYNC
(29.4 kHz)		FSYNC
(44.1 kHz)		FSYNC
(88.2 kHz)		FSYNC
(176.4 kHz)
16ReservedReserved0.35280.47040.70561.41122.8224
24Reserved0.35280.52920.70561.05842.11684.2336
32Reserved0.47040.70560.94081.41122.82245.6448
480.35280.70561.05841.41122.11684.23368.4672
640.47040.94081.41121.88162.82245.644811.2896
960.70561.41122.11682.82244.23368.467216.9344
1280.94081.88162.82243.76325.644811.289622.5792
1921.41122.82244.23365.64488.467216.9344Reserved
2561.88163.76325.64487.526411.289622.5792Reserved
3842.82245.64488.467211.289616.9344ReservedReserved
5123.76327.526411.289615.052822.5792ReservedReserved

In the master mode of operation, the device uses the MD1 pin (as the system clock, MCLK) as the reference input clock source with a supported system clock frequency option of either 256 × fS or 512 × fS as configured using the MD0 pin. Master mode supports fS rates of 44.1 kHz and 48 kHz. Table 8-5 shows the system clock selection for the master mode using the MD0 pin.

Table 8-5 System Clock Selection for the Master Mode
MD0SYSTEM CLOCK SELECTION (Valid for Master Mode Only)
LOWSystem clock with frequency 256 × fS connected to the MD1 pin as MCLK
HIGHSystem clock with frequency 512 × fS connected to the MD1 pin as MCLK

See Table 8-7 and Table 8-20 for the MD0 and MD1 pin function in the slave mode of operation.