10 Power Supply Recommendations

The power-supply sequence between the IOVDD and AVDD rails can be applied in any order. However, do not provide any clocks until the IOVDD and AVDD supply voltage settles to a stable and supported operating voltage range. Provide the clocks (FSYNC and BCLK) only when all hardware control pins (MSZ, MD0, MD1, and FMT0) are driven to the voltage level for the device desired mode of operation.

For the supply power-up requirement, t₁ and t₂ must be at least 100 µs. For the supply power-down requirement, t₃ and t₄ must be at least 10 ms. This timing (as shown in Figure 10-1) allows the device to ramp down the volume on the record data, power down the analog and digital blocks, and put the device into hardware shutdown mode.

Figure 10-1 Power-Supply Sequencing Requirement Timing Diagram

Make sure that the supply ramp rate is slower than 1 V/µs and that the wait time between a power-down and a power-up event is at least 100 ms. All digital input pins must be held at valid input levels and not toggling during supply sequencing.