SLES142B JUNE   2005  – July 2016 PCM1803A

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
      1. 6.6.1 Typical Curves of Internal Filter
        1. 6.6.1.1 Decimation Filter Frequency Response
        2. 6.6.1.2 Low-Cut Filter Frequency Response
      2. 6.6.2 Typical Performance Curves
      3. 6.6.3 Output Spectrum
      4. 6.6.4 Supply Current
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Hardware Control
      2. 7.3.2 Power-On-Reset Sequence
      3. 7.3.3 System Clock
    4. 7.4 Device Functional Modes
      1. 7.4.1 Serial Audio Data Interface
        1. 7.4.1.1 Interface Mode
          1. 7.4.1.1.1 Master Mode
          2. 7.4.1.1.2 Slave Mode
        2. 7.4.1.2 Data Format
        3. 7.4.1.3 Interface Timing
      2. 7.4.2 Synchronization With Digital Audio System
      3. 7.4.3 Power Down
      4. 7.4.4 HPF Bypass
      5. 7.4.5 Oversampling Ratio Control
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Control Pins
        2. 8.2.2.2 DSP or Audio Processor
        3. 8.2.2.3 Input Filters
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 VCC, VDD Pins
      2. 10.1.2 AGND, DGND Pins
      3. 10.1.3 VINL, VINR Pins
      4. 10.1.4 VREF1 Pin
      5. 10.1.5 VREF2 Pin
      6. 10.1.6 DOUT Pin
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

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5 Pin Configuration and Functions

DB Package
20-Pin SSOP
Top View

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
AGND 6 – Analog GND
BCK 11 I/O Audio data bit clock input/output(1)
BYPAS 8 I HPF bypass control. LOW: Normal mode (DC reject); HIGH: Bypass mode (through)(2)
DGND 13 – Digital GND
DOUT 12 O Audio data digital output
FMT0 17 I Audio data format select input 0. See Data Format.(2)
FMT1 18 I Audio data format select input 1. See Data Format.(2)
LRCK 10 I/O Audio data latch enable input/output(1)
MODE0 19 I Mode select input 0. See Data Format.(2)
MODE1 20 I Mode select input 1. See Data Format.(2)
OSR 16 I Oversampling ratio select input. LOW: ×64 fS, HIGH: ×128 fS(2)
PDWN 7 I Power-down control, active-low (2)
SCKI 15 I System clock input: 256 fS, 384 fS, 512 fS, or 768 fS(3)
TEST 9 I Test, must be connected to DGND(2)
VCC 5 – Analog power supply, 5-V
VDD 14 – Digital power supply, 3.3-V
VINL 1 I Analog input, L-channel
VINR 2 I Analog input, R-channel
VREF1 3 – Reference-voltage-1 decoupling capacitor
VREF2 4 – Reference-voltage-2 decoupling capacitor
(1) Schmitt-trigger input
(2) Schmitt-trigger input with internal pulldown (50 kΩ, typically), 5-V tolerant
(3) Schmitt-trigger input, 5-V tolerant