The audio serial interface for the PCM175x devices consists of a 3-wire synchronous serial port. The interface includes LRCK (pin 3), BCK (pin 1), and DATA (pin 2). The BCK pin is the serial audio bit clock, and it is used to clock the serial data present on the DATA pin into the serial shift register of the audio interface. Serial data is clocked into the PCM175x on the rising edge of the BCK pin. The LRCK pin is the serial audio left and right word clock. This pin is used to latch serial data into the internal registers of the serial audio interface.
Both the LRCK and BCK pins should be synchronous to the system clock. Ideally, TI recommendeds that the LRCK and BCK pins be derived from the system clock input, SCK. The LRCK pin is operated at the sampling frequency, fS. The BCK pin can be operated at 32, 48, or 64 times the sampling frequency for standard (right-justified) format, and 32 times the sampling frequency of the BCK pin is limited to 16-bit right-justified format only. The BCK pin can be operated at 48 or 64 times the sampling frequency for the I2S and left-justified formats. 48 times the sampling frequency of BCK is limited to 192/384/768 fS SCKI.
Internal operation of the PCM175x devices is synchronized with the LRCK pin. Accordingly, internal operation is held when the sampling rate clock of the LRCK pin is changed or when the SCK pin and/or BCK pin is interrupted for a 3-bit clock cycle or longer. If th SCK, BCK, and LRCK pins are provided continuously after this held condition, the internal operation is re-synchronized automatically in a period of less than 3/fS. External resetting is not required.