ZHCSK28E April   2003  – July 2019 PCM1753 , PCM1754 , PCM1755

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      功能方框图
  4. 4 修订历史记录
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 System Clock Input Timing
    7. 7.7 Audio Interface Timing
    8. 7.8 Control Interface Timing Requirements
    9. 7.9 Typical Characteristics
      1. 7.9.1 Digital Filter (De-Emphasis Off)
      2. 7.9.2 Analog Dynamic Performance (Supply Voltage Characteristics)
      3. 7.9.3 Analog Dynamic Performance (Temperature Characteristics)
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 System Clock and Reset Functions
        1. 8.3.1.1 System Clock Input
        2. 8.3.1.2 Power-On Reset Functions
      2. 8.3.2 Audio Serial Interface
        1. 8.3.2.1 Audio Data Formats and Timing
      3. 8.3.3 Zero Flag (PCM1754)
      4. 8.3.4 Zero Flag (PCM1753)
      5. 8.3.5 Zero Flag Outputs
      6. 8.3.6 Analog Outputs
        1. 8.3.6.1 VCOM Output
    4. 8.4 Device Functional Modes
      1. 8.4.1 Hardware Control (PCM1754)
      2. 8.4.2 Oversampling Rate Control (PCM1754)
    5. 8.5 Programming
      1. 8.5.1 Software Control (PCM1753/55)
        1. 8.5.1.1 Register Write Operation
    6. 8.6 Register Maps
      1. 8.6.1 Mode Control Registers (PCM1753/55)
        1. 8.6.1.1 User-Programmable Mode Controls
        2. 8.6.1.2 Register Definitions
          1. 8.6.1.2.1  ATx[7:0]: Digital Attenuation Level Setting
          2. 8.6.1.2.2  MUTx: Soft Mute Control
          3. 8.6.1.2.3  OVER: Oversampling Rate Control
          4. 8.6.1.2.4  SRST: Reset
          5. 8.6.1.2.5  DACx: DAC Operation Control
          6. 8.6.1.2.6  DM12: Digital De-Emphasis Function Control
          7. 8.6.1.2.7  DMF[1:0]: Sampling Frequency Selection for the De-Emphasis Function
          8. 8.6.1.2.8  FMT[2:0]: Audio Interface Data Format
          9. 8.6.1.2.9  FLT: Digital Filter Rolloff Control
          10. 8.6.1.2.10 DREV: Output Phase Select
          11. 8.6.1.2.11 ZREV: Zero Flag Polarity Select
          12. 8.6.1.2.12 AZRO: Zero Flag Function Select
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Design Parameters
        2. 9.2.1.2 Power Supplies and Grounding
        3. 9.2.1.3 D/A Output Filter Circuits
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Total Harmonic Distortion + Noise
        2. 9.2.2.2 Dynamic Range
        3. 9.2.2.3 Idle Channel Signal-to-Noise Ratio (SNR)
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 相关文档　
    2. 12.2 相关链接
    3. 12.3 接收文档更新通知
    4. 12.4 社区资源
    5. 12.5 商标
    6. 12.6 静电放电警告
    7. 12.7 Glossary
  13. 13机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

8.3.1.1 System Clock Input

The PCM175x devices require a system clock for operating the digital interpolation filters and multilevel delta-sigma modulators. The system clock is applied at the SCK input (pin 16). Table 1 lists examples of system clock frequencies for common audio sampling rates.

Figure 20 shows and the System Clock Input Timing table lists he timing requirements for the system clock input. For optimal performance, use a clock source with low phase-jitter and noise. TI's PLL170x family of multiclock generators is an excellent choice for providing the PCM175x system clock.

Table 1. System Clock Rates for Common Audio Sampling Frequencies

SAMPLING FREQUENCY SYSTEM CLOCK FREQUENCY (fSCLK) (MHz)
128 fS 192 fS 256 fS 384 fS 512 fS 768 fS 1152 fS
8 kHz 1.024 1.536 2.048 3.072 4.096 6.144 9.216
16 kHz 2.048 3.072 4.096 6.144 8.192 12.288 18.432
32 kHz 4.096 6.144 8.192 12.288 16.384 24.576 36.864
44.1 kHz 5.6448 8.4672 11.2896 16.9344 22.5792 33.8688  (1)
48 kHz 6.144 9.216 12.288 18.432 24.576 36.864  (1)
88.2 kHz 11.2896 16.9344 22.5792 33.8688 45.1584  (1)  (1)
96 kHz 12.288 18.432 24.576 36.864 49.152  (1)  (1)
192 kHz 24.576 36.864  (1)  (1)  (1)  (1)  (1)
(1) This system clock rate is not supported for the given sampling frequency.
PCM1753 PCM1754 PCM1755 sys_clock_input_timing_les254.gifFigure 20. System Clock Input Timing