ZHCSJO8 May   2019 OPA818

ADVANCE INFORMATION for pre-production products; subject to change without notice.  

  1. 特性
  2. 应用
    1.     高速光学前端
  3. 说明
    1.     光电二极管电容与 3dB 带宽间的关系
  4. 修订历史记录
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics: VS = ±5 V
    6. 6.6 Typical Characteristics: VS = ±5 V
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input and ESD Protection
      2. 7.3.2 Feedback Pin
      3. 7.3.3 Decompensated Architecture With Wide Gain-Bandwidth Product
      4. 7.3.4 Low Input Capacitance
    4. 7.4 Device Functional Modes
      1. 7.4.1 Split-Supply Operation (+4/–2 V to ±6.5 V)
      2. 7.4.2 Single-Supply Operation (6 V to 13 V)
  8. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Wideband, Noninverting Operation
      2. 8.1.2 Wideband, Transimpedance Design Using OPA818
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Thermal Considerations
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 接收文档更新通知
    2. 11.2 社区资源
    3. 11.3 商标
    4. 11.4 静电放电警告
    5. 11.5 Glossary
  12. 12机械、封装和可订购信息
    1. 12.1 Package Option Addendum
      1. 12.1.1 Packaging Information


机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)

Detailed Design Procedure

Designs that require high bandwidth from a large area detector with relatively high transimpedance gain benefit from the low input voltage noise of the OPA818. This input voltage noise is peaked up over frequency by the diode source capacitance, and can, in many cases, become the limiting factor to input sensitivity. Figure 14 shows the transimpedance circuit with the parameters as defined in Design Requirements. To use the Microsoft Excel™ calculator available at What You Need To Know About Transimpedance Amplifiers – Part 1 to help with the component selection, total input capacitance, CTOT,needs to be determined. CTOT is referred as CIN in the calculator. CTOT is the sum of CD, CDIFF, and CCM which is 7.4 pF. Using this value of CTOT, and the targeted closed-loop bandwidth (f–3dB) of 24 MHz and transimpedance gain of 100 kΩ results in a need for an amplifier with approximately 2.68 GHz GBWP and a feedback capacitance (CF) of 0.092 pF as shown in Figure 15. These results are for a Butterworth response with a Q = 0.707 and a phase margin of approximately 65° which corresponds to 4.3% overshoot.

OPA818 SBOS940_OPA818_Apps-TIA-typ-calculator.gifFigure 15. Results of Inputting Design Parameters in the TIA Calculator

With OPA818's 2.7 GHz GBWP, it will be a suitable amplifier for the design requirements. A challenge with the calculated component results is practically realizing a 0.092 pF capacitor. Such a small capacitor can be realized by using a capacitive tee network formed by C1, C2, and CT such as that shown in Figure 14. The equivalent capacitance, CEQ, of the tee network is given by Equation 2.

Equation 2. OPA818 SBOS940_OPA818_Eq-Tee-network.gif

The tee network forms a capacitive attenuator from input to output with C1 and CT, and from output to input with C2 and CT. With the value of CT being higher than C1 or C2, only a fraction of the output signal is seen by C1. This results in a much smaller shunting current provided to the input through C1 and this reduced shunting current effect is equivalent to how a much smaller capacitor behaves (at a fixed frequency, smaller capacitor has higher impedance and thus reduced current). It is recommended to keep the same level of attenuation from input to output and vice versa. To find the appropriate capacitor values for the tee network, chose an arbitrarily low but practically realizable and equal values for capacitors C1 and C2, set CEQ = CTOT, and use Equation 3 to get the value of the tunable capacitor, CT. The values of capacitors C1, C2, and CT in Figure 14 were determined using this process.

Equation 3. OPA818 SBOS940_OPA818_Eq-Tee-network-CT-calc.gif

Figure 16 shows the TINA simulated closed-loop bandwidth response of the circuit in Figure 14. The circuit was designed for f–3dB = 24 MHz and the simulated closed-loop 3-dB frequency is 24.6 MHz with about 0.1 dB peaking. The OPA818 TINA model models the input common-mode and differential capacitors so they should not be added externally when simulating in TINA. The noise simulation of the TIA circuit is shown in Figure 17. The output referred voltage noise is shown on the Y-axis to the left and the input referred current noise, which is essentially output referred voltage noise divided by the transimpedance gain of 100k, is shown on the secondary Y-axis to the right. The simulation results are fairly accurate because the OPA818 TINA model closely models the voltage and current noise performance of the amplifier. The flat-band output voltage noise is 41 nV/√Hz that is equivalent to 0.41 pA/√Hz of input referred current noise. The noise in relatively low frequency region where the noise gain of the amplifier is 1 V/V is dominated by the thermal noise of the 100 kΩ resistor (40.7 nV/√Hz at 27°C). At mid frequencies beyond the zero formed by RF and CTOT, the noise gain of the amplifier amplifies the voltage noise of the amplifier. The amplifier's noise starts to become the dominant noise contributor from this frequency onwards before the output noise starts to roll off at frequencies beyond the 3-dB closed-loop bandwidth. When looked at integrated root-mean-square (RMS) noise, the mid-frequency noise will be a significant contributor and hence using a 2.2 nV/√Hz low-noise amplifier like OPA818 is advantageous to minimize total RMS noise in the system.