ZHCSKG0J October   2019  – April 2021 OPA2607 , OPA607

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Operating Voltage
      2. 8.3.2 Rail-to-Rail Output and Driving Capacitive Loads
      3. 8.3.3 Input and ESD Protection
      4. 8.3.4 Decompensated Architecture with Wide Gain-Bandwidth Product
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal Operating Mode
      2. 8.4.2 Power Down Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 100-kΩ Gain Transimpedance Design
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Noninverting Gain of 3 V/V
      3. 9.2.3 High-Input Impedance (Hi-Z), High-Gain Signal Front-End
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Detailed Design Procedure
        3. 9.2.3.3 Application Curves
      4. 9.2.4 Low-Cost, Low Side, High-Speed Current Sensing
        1. 9.2.4.1 Design Requirements
        2. 9.2.4.2 Detailed Design Procedure
        3. 9.2.4.3 Application Curves
      5. 9.2.5 Ultrasonic Flow Meters
        1. 9.2.5.1 Design Requirements
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Examples
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Related Links
    4. 12.4 Receiving Notification of Documentation Updates
    5. 12.5 支持资源
    6. 12.6 Trademarks
    7. 12.7 Electrostatic Discharge Caution
    8. 12.8 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

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7.5 Electrical Characteristics

At TA = 25°C, VS = 2.2 V to 5.5 V, G = 6 V/V(5), RF = 5 kΩ, CF = 2.5 pF, VCM = (VS / 2) – 0.5 V, CL = 10 pF,              RL = 10 kΩ connected to (VS / 2) – 0.5 V, and, PD connected to (VS+) (unless otherwise noted)(1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OFFSET VOLTAGE
VOS Input offset voltage –0.6 0.12 0.6 mV
Input offset voltage TA = –40°C to +125°C –0.7 0.12 0.7
dVOS/dT Input offset voltage drift TA = –40°C to +125°C  ±0.3 ±1.5 µV/°C
PSRR Power-supply rejection ratio VS = 2.2 V to 5.5 V 95 120 dB
INPUT VOLTAGE RANGE
VCM Common-mode voltage range (VS–)  (VS+)–1.1 V
CMRR Common-mode rejection ratio(3) (VS–) < VCM < (VS+) – 1.1 V  90 100 dB
INPUT BIAS CURRENT
IB Input bias current(2) ±3 ±10 pA
TA = –40℃ to 125℃ See Fig. 29
IOS Input offset current(2) ±3 ±10
NOISE
Input voltage noise (peak-to-peak) f = 0.1 Hz to 10 Hz 1.6 µVPP
eN Input voltage noise density f = 10 kHz, 1/f corner at 1 kHz  3.8 nV/√Hz
iN Input current noise density f = 1 kHz 46 fA/√Hz
INPUT IMPEDANCE
CIN Differential 11.5 pF
Common-mode 5.5
OPEN-LOOP GAIN
AOL Open-loop voltage gain(3) (VS–) + 400 mV < VOUT < (VS+) – 400 mV 110 130 dB
Phase margin 65 °
AC Characteristics (VS = 5 V)
SSBW Small-signal bandwidth VOUT = 20 mVpp 9 MHz
GBW Gain-bandwidth product G = 20 V/V 50
SR Slew rate 3-V output step (10-90%), VOCM = mid-supply 24 V/µs
tS Settling time To 0.1%, 3-V step, G = 40, VOCM = mid-supply 1 µs
To 0.01%, 3-V step, G = 40, VOCM = mid-supply 1.8
Overdrive recovery time VIN+ × Gain > VS  0.3 µs
THD + N Total Harmonic Distortion + Noise(6) VOUT = 2 VPP, f = 1 kHz , RL = 10 kΩ -103 dB
VOUT = 2 VPP, f = 20 kHz , RL = 10 kΩ -91.5
VOUT = 2 VPP, f = 1 kHz , RL = 1 kΩ -96
VOUT = 2 VPP, f = 20 kHz , RL = 1 kΩ -72.8
HD2 Second-order harmonic distortion VOUT = 2 VPP  f = 20 kHz -105 dBc
HD3 Third-order harmonic distortion VOUT = 2 VPP   f = 20 kHz -95
Channel-to-channel crosstalk VOUT = 2 VPP, f = 100 kHz -114 dBc
OUTPUT
  Output voltage swing from supply rails 8 12 mV
TA = – 40℃ to +125℃ 12
ISC Output Short-circuit current 60 mA
ZO Open-loop output impedance f = 1 MHz 500 Ω
POWER SUPPLY
IQ Quiescent current per amplifier IO = 0 mA 900 1100 µA
IO = 0 mA, TA = –40°C to +125°C 1200
POWER DOWN (Device Enabled When Floating)
Power Down quiescent current per amplifier(4) PD = VS– 750 1000 nA
Power Down pin bias current per amplifier(7) PD = VS– –750 –1000
Enable voltage threshold Logic-High threshold 0.7 x VS V
Disable voltage threshold Logic-Low threshold 0.2 x VS
tON Turn-on time delay(2) 10 15 µs
tOFF Turn-off time delay 0.5
(1) Parameters with minimum or maximum specification limits are 100% production tested at 25ºC, unless otherwise noted. Over temperature limits are based on characterization and statistical analysis.
(2) Specified by design and characterization or both ; not production tested.
(3) Production Tested at VS = 5.5V
(4) In Power Down mode current drawn by the opamp is equal to the bias current sourced on the PD pin
(5) All Gains (G) mentioned are in V/V unless otherwise noted.
(6) Lowpass-filter bandwidth is 92kHz for f = 20 kHz and 20 kHz for f = 1 kHz.
(7) Negative value of the Power Down bias current indicates current being sourced from the opamp's PD pin towards external circuit.