ZHCSKG0J October   2019  – April 2021 OPA2607 , OPA607

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Operating Voltage
      2. 8.3.2 Rail-to-Rail Output and Driving Capacitive Loads
      3. 8.3.3 Input and ESD Protection
      4. 8.3.4 Decompensated Architecture with Wide Gain-Bandwidth Product
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal Operating Mode
      2. 8.4.2 Power Down Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 100-kΩ Gain Transimpedance Design
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Noninverting Gain of 3 V/V
      3. 9.2.3 High-Input Impedance (Hi-Z), High-Gain Signal Front-End
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Detailed Design Procedure
        3. 9.2.3.3 Application Curves
      4. 9.2.4 Low-Cost, Low Side, High-Speed Current Sensing
        1. 9.2.4.1 Design Requirements
        2. 9.2.4.2 Detailed Design Procedure
        3. 9.2.4.3 Application Curves
      5. 9.2.5 Ultrasonic Flow Meters
        1. 9.2.5.1 Design Requirements
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Examples
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Related Links
    4. 12.4 Receiving Notification of Documentation Updates
    5. 12.5 支持资源
    6. 12.6 Trademarks
    7. 12.7 Electrostatic Discharge Caution
    8. 12.8 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

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6 Pin Configuration and Functions

GUID-EE247D21-0E7A-4C0D-B0BD-E9A52E432D32-low.gifFigure 6-1 DBV Package
5-Pin SOT-23
Top View
GUID-12672F5D-1472-4A75-A1DF-83C3083FBDF0-low.gifFigure 6-2 DCK Package
6-Pin SC70
Top View
Pin Functions – Single Channel
PIN I/O DESCRIPTION
NAME DBV DCK
IN– 4 3 I Inverting input
IN+ 3 1 I Non inverting input
OUT 1 4 O Output
PD — 5 I Power down (can be left floating)
VS– 2 2 — Negative supply or ground (for single-supply operation)
VS+ 5 6 — Positive supply
GUID-97E87C33-5652-4DF4-AD69-F7AFF3ECED63-low.gifFigure 6-3 OPA2607 D, DGK Package
8-Pin SOIC, VSSOP
Top View
GUID-943873BF-6DFE-48E6-A6E5-8088054DADBF-low.gifFigure 6-4 OPA2607 RUG Package
10-Pin X2QFN
Top View
Pin Functions – Dual Channel
PIN I/O DESCRIPTION
NAME D, DGK RUG
IN1– 2 2 I Inverting input, channel 1
IN1+ 3 3 I Noninverting input, channel 1
IN2– 6 8 I Inverting input, channel 2
IN2+ 5 7 I Noninverting input, channel 2
OUT1 1 1 O Output, channel 1
OUT2 7 9 O Output, channel 2
VS– 4 5 — Negative (lowest) supply or ground (for single-supply operation)
VS+ 8 10 — Positive (highest) supply
PD1 — 4 I Low = amplifier 1 disabled, high = amplifier 1 enabled; see the Power Down Mode section for more information.
PD2 — 6 I Low = amplifier 2 disabled, high = amplifier 2 enabled; see the Power Down Mode section for more information.