Figure 11-1 shows a typical layout around the OPA3S2859-EP based on the evaluation module. The smallest decoupling capacitors were placed as close as possible to the DUT with wide metal area to minimize inductance. Special attention was placed on the feedback network layout to optimize the design for a typical application using 1 kΩ, 10 kΩ, and 100 kΩ feedback resistors. Please see Figure 11-2 for more details. The black colored areas under the input and feedback traces show the voids cut in the ground plane underneath the traces to minimize capacitance to ground as much as possible.

Figure 11-2 shows an example of a feedback network from the evaluation module optimized to reduce the capacitive coupling between the feedback and output traces. Ground plane is poured between each of the feedback traces and component footprints as much as possible for the best isolation. A small isoation resistor (RISO) in connected between the output and feedback trace to help isolate the trace capacitance from being directly connected to the DUT output. Additionally, the ground plane is removed from under the feedback trace to further reduce the parasitic capacitance to ground created by the additional trace length required for the feedback network.