| Offset Voltage Production Distribution |
Figure 1, Figure 2, Figure 3
|
| Offset Voltage Drift Distribution |
Figure 4
|
| Offset Voltage vs Temperature |
Figure 5
|
| Offset Voltage vs Common-Mode Voltage |
Figure 6, Figure 7, Figure 8
|
| Offset Voltage vs Power Supply |
Figure 9
|
| Open-Loop Gain and Phase vs Frequency |
Figure 10
|
| Closed-Loop Gain and Phase vs Frequency |
Figure 11
|
| Input Bias Current vs Common-Mode Voltage |
Figure 12
|
| Input Bias Current vs Temperature |
Figure 13
|
| Output Voltage Swing vs Output Current (maximum supply) |
Figure 14, Figure 15
|
| CMRR and PSRR vs Frequency |
Figure 16
|
| CMRR vs Temperature |
Figure 17
|
| PSRR vs Temperature |
Figure 18
|
| 0.1-Hz to 10-Hz Noise |
Figure 19
|
| Input Voltage Noise Spectral Density vs Frequency |
Figure 20
|
| THD+N Ratio vs Frequency |
Figure 21
|
| THD+N vs Output Amplitude |
Figure 22
|
| Quiescent Current vs Supply Voltage |
Figure 23
|
| Quiescent Current vs Temperature |
Figure 24
|
| Open Loop Gain vs Temperature |
Figure 25
|
| Open Loop Output Impedance vs Frequency
|
Figure 26
|
| Small Signal Overshoot vs Capacitive Load (100-mV output step) |
Figure 27, Figure 28
|
| No Phase Reversal |
Figure 29
|
| Positive Overload Recovery |
Figure 30
|
| Negative Overload Recovery |
Figure 31
|
| Small-Signal Step Response (100 mV) |
Figure 32, Figure 33
|
| Large-Signal Step Response |
Figure 34
|
| Settling Time |
Figure 35, Figure 36, ,
|
| Short-Circuit Current vs Temperature |
Figure 37
|
| Maximum Output Voltage vs Frequency |
Figure 38
|
| Propagation Delay Rising Edge |
Figure 39
|
| Propagation Delay Falling Edge |
Figure 40
|