ZHCSE47A September   2015  – June 2022 OPA1688

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 EMI Rejection
      2. 8.3.2 Phase-Reversal Protection
      3. 8.3.3 Capacitive Load and Stability
    4. 8.4 Device Functional Modes
      1. 8.4.1 Common-Mode Voltage Range
      2. 8.4.2 Electrical Overstress
      3. 8.4.3 Overload Recovery
  9. 9 Applications and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Headphone Amplifier Circuit Configuration
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
        1. 12.1.1.1 PSpice® for TI
        2. 12.1.1.2 TINA-TI™ Simulation Software (Free Download)
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 接收文档更新通知
    4. 12.4 支持资源
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 术语表
  13. 13Mechanical, Packaging, and Orderable Information

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6 Pin Configuration and Functions

GUID-80E792B5-AADB-4B29-A116-63ABB97CF996-low.gifFigure 6-1 D (SOIC-8) Package, Top View
GUID-E5ABEDC8-EA63-4648-8959-C746D7B96DC3-low.gifFigure 6-2 DRG (WSON-8) Package, Top View
Table 6-1 Pin Functions
PIN TYPE DESCRIPTION
NAME NO.
D
(SOIC)		 DRG
(WSON)
–IN A 2 8 Input Inverting input, channel A
–IN B 6 5 Input Inverting input, channel B
+IN A 3 1 Input Noninverting input, channel A
+IN B 5 4 Input Noninverting input, channel B
OUT A 1 7 Output Output, channel A
OUT B 7 6 Output Output, channel B
V– 4 3 Power Negative (lowest) power supply
V+ 8 2 Power Positive (highest) power supply