ZHCSDW6A June   2015  – July 2015 ONET1130EP

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 修订历史记录
  5. 5 说明（续）
  6. 6 Pin Configuration and Function
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 DC Electrical Characteristics
    6. 7.6 Transmitter AC Electrical Characteristics
    7. 7.7 Receiver AC Electrical Characteristics
    8. 7.8 Timing Requirements
    9. 7.9 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Transmitter
        1. 8.3.1.1 Equalizer
        2. 8.3.1.2 Modulator Driver
        3. 8.3.1.3 Modulation Current Generator
        4. 8.3.1.4 DC Offset Cancellation and Cross Point Control
        5. 8.3.1.5 Transmitter Loopback (Electrical Loopback)
        6. 8.3.1.6 Bias Current Generation and APC Loop
        7. 8.3.1.7 Laser Safety Features and Fault Recovery Procedure
      2. 8.3.2 Receiver
        1. 8.3.2.1 Equalizer
        2. 8.3.2.2 DC Offset Cancellation and Cross Point Control
        3. 8.3.2.3 Output Driver
        4. 8.3.2.4 Receiver Loopback (Optical Loopback)
        5. 8.3.2.5 Loss of Signal Detection
      3. 8.3.3 Analog Block
        1. 8.3.3.1 Analog Reference and Temperature Sensor
        2. 8.3.3.2 Power-On Reset
        3. 8.3.3.3 Analog to Digital Converter
        4. 8.3.3.4 2-Wire Interface and Control Logic
        5. 8.3.3.5 Bus Idle
        6. 8.3.3.6 Start Data Transfer
        7. 8.3.3.7 Stop Data Transfer
        8. 8.3.3.8 Data Transfer
      4. 8.3.4 Acknowledge
    4. 8.4 Device Functional Modes
      1. 8.4.1 Differential Transmitter Output
      2. 8.4.2 Single-Ended Transmitter Output
    5. 8.5 Programming
    6. 8.6 Register Mapping
      1. 8.6.1 R/W Control Registers
        1. 8.6.1.1 Core Level Register 0 (offset = 0100 0001 [reset = 41h]
        2. 8.6.1.2 Core Level Register 1 (offset = 0000 0000) [reset = 0h]
        3. 8.6.1.3 Core Level Register 2 (offset = 0000 0000 ) [reset = 0h]
        4. 8.6.1.4 Core Level Register 3 (offset = 0000 0000) [reset = 0h]
      2. 8.6.2 RX Registers
        1. 8.6.2.1 RX Register 4 (offset = 0000 0000) [reset = 0h]
        2. 8.6.2.2 RX Register 5 (offset = 0000 0000) [reset = 0h]
        3. 8.6.2.3 RX Register 6 (offset = 0000 0000) [reset = 0h]
        4. 8.6.2.4 RX Register 7 (offset = 0000 0000) [reset = 0h]
        5. 8.6.2.5 RX Register 8 (offset = 0000 0000) [reset = 0h]
        6. 8.6.2.6 RX Register 9 (offset = 0000 0000) [reset = 0h]
      3. 8.6.3 TX Registers
        1. 8.6.3.1 TX Register 10 (offset = 0000 0000) [reset = 0h]
        2. 8.6.3.2 TX Register 11 (offset = 0000 0000) [reset = 0h]
        3. 8.6.3.3 TX Register 12 (offset = 0000 0000) [reset = 0h]
        4. 8.6.3.4 TX Register 13 (offset = 0h) [reset = 0]
        5. 8.6.3.5 TX Register 14 (offset = 0000 0000) [reset = 0h]
        6. 8.6.3.6 TX Register 15 (offset = 0000 0000) [reset = 0h]
        7. 8.6.3.7 TX Register 16 (offset = 0000 0000) [reset = 0h]
        8. 8.6.3.8 TX Register 17 (offset = 0000 0000) [reset = 0h]
        9. 8.6.3.9 TX Register 18 (offset = 0000 0000) [reset = 0h]
      4. 8.6.4 Reserved Registers
        1. 8.6.4.1 Reserved Registers19-39
      5. 8.6.5 Read Only Registers
        1. 8.6.5.1 Core Level Register 40 (offset = 0000 0000) [reset = 0h]
        2. 8.6.5.2 Core Level Register 41 (offset = 0000 0000) [reset = 0h]
        3. 8.6.5.3 RX Registers 42 (offset = 0000 0000) [reset = 0h]
        4. 8.6.5.4 TX Register 43 (offset = 0000 0000) [reset = 0h]
      6. 8.6.6 Adjustment Registers
        1. 8.6.6.1 Adjustment Registers 44-55
        2. 8.6.6.2 Adjustment Registers 52-55
  9. 9 Application Information and Implementations
    1. 9.1 Application Information
    2. 9.2 Typical Application, Transmitter Differential Mode
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
      4. 9.2.4 Typical Application, Transmitter Single-Ended Mode
        1. 9.2.4.1 Design Requirements
        2. 9.2.4.2 Detailed Design Procedure
        3. 9.2.4.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 社区资源
    2. 12.2 商标
    3. 12.3 静电放电警告
    4. 12.4 Glossary
  13. 13机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

6 Pin Configuration and Function

RSM PACKAGE
32 PIN VQFN
(TOP VIEW)
ONET1130EP po_SLLSEO4.gif

Pin Functions

NUMBER NAME Type DESCRIPTION
AMP 16 Analog-in Output amplitude control. Output amplitude can be adjusted by applying a voltage of 0 to 2 V to this pin. Leave open when not used.
BIAS 10 Analog Sinks or sources the bias current for the laser in both APC and open loop modes.
COMP 23 Analog Compensation pin used to control the bandwidth of the APC loop. Connect a 0.01-µF capacitor to ground.
GND 3, 6, 19, 22 Supply Circuit ground.
MONB 2 Analog-out Bias current monitor.
MONP 8 Analog-out Photodiode current monitor.
NC 1, 9, 25 Do not connect.
PD 7 Analog Photodiode input. Pin can source or sink current dependent on register setting.
RX_DIS 26 Digital-in Disables the receiver output buffer when set to a high level. Includes a 250-kΩ pull-up resistor to VCC. Ground the pin to enable the output. This is an ORed function with the RXOUT_DIS bit (bit 6 in register 4). This pin is 3.3-V tolerant.
RX_LOS 24 Digital-out Receiver loss of signal. High level indicates that the receiver input signal amplitude is below the programmed threshold level. Open drain output. Requires an external 4.7-kΩ to 10-kΩ pull-up resistor to VCC for proper operation. This pin is 3.3-V tolerant.
RXIN+ 20 Analog-in Non-inverted receiver data input. On-chip differentially 100 Ω terminated to RXIN–. Must be AC coupled.
RXIN- 21 Analog-in Inverted receiver data input. On-chip differentially 100 Ω terminated to RXIN+. Must be AC coupled.
RXOUT– 28 CML-out Inverted receiver data output. 45 Ω back-terminated to VCC.
RXOUT+ 29 CML-out Non-inverted data output. 45 Ω back-terminated to VCC.
SDA 17 Digital-in/out 2-wire interface serial data input. Requires an external 4.7-kΩ to10-kΩ pull-up resistor to VCC. This pin is 3.3-V tolerant.
SCK 18 Digital-in 2-wire interface serial clock input. Requires an external 4.7-kΩ to10-kΩ pull-up resistor to VCC. This pin is 3.3-V tolerant.
TX_DIS 32 Digital-in Disables both bias and modulation currents when set to high state. Includes a 250-kΩ pull-up resistor to VCC. Requires an external 4.7 kΩ to 10 kΩ pull-up resistor to VCC for proper operation Toggle to reset a fault condition. This is an ORed function with the TXBIASEN bit (bit 2 in register 1). This pin is 3.3-V tolerant.
TXIN+ 4 Analog-in Non-inverted transmitter data input. On-chip differentially 100 Ω terminated to TXIN–. Must be AC coupled.
TXIN– 5 Analog-in Inverted transmitter data input. On-chip differentially 100 Ω terminated to TXIN+. Must be AC coupled.
TX_FLT 31 Digital-out Transmitter fault detection flag. High level indicates that a fault has occurred. Open drain output. Requires an external 4.7 kΩ to 10 kΩ pull-up resistor to VCC for proper operation. This pin is 3.3-V tolerant.
TXOUT– 12 CML-out Inverted transmitter data output. Internally terminated in single-ended operation mode.
TXOUT+ 13 CML-out Non-Inverted transmitter data output.
VCC_RX 27, 30 Supply 2.5 V ± 5% supply for the receiver.
VCC_TX 11, 14 Supply 2.5 V ± 5% supply for the transmitter.
VDD 15 Supply 2.5 V ± 5% supply for the digital circuitry.
Exposed Pad EP Exposed die pad. Solder to the PCB.