SPRS563G September   2008  – June 2014 OMAP-L137

PRODUCTION DATA.  

  1. 1 OMAP-L137 Low-Power Applications Processor
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Overview
    1. 3.1 Device Characteristics
    2. 3.2 Device Compatibility
    3. 3.3 ARM Subsystem
      1. 3.3.1 ARM926EJ-S RISC CPU
      2. 3.3.2 CP15
      3. 3.3.3 MMU
      4. 3.3.4 Caches and Write Buffer
      5. 3.3.5 Advanced High-Performance Bus (AHB)
      6. 3.3.6 Embedded Trace Macrocell (ETM) and Embedded Trace Buffer (ETB)
      7. 3.3.7 ARM Memory Mapping
    4. 3.4 DSP Subsystem
      1. 3.4.1 C674x DSP CPU Description
      2. 3.4.2 DSP Memory Mapping
        1. 3.4.2.1 ARM Internal Memories
        2. 3.4.2.2 External Memories
        3. 3.4.2.3 DSP Internal Memories
        4. 3.4.2.4 C674x CPU
    5. 3.5 Memory Map Summary
    6. 3.6 Pin Assignments
      1. 3.6.1 Pin Map (Bottom View)
    7. 3.7 Terminal Functions
      1. 3.7.1  Device Reset and JTAG
      2. 3.7.2  High-Frequency Oscillator and PLL
      3. 3.7.3  Real-Time Clock and 32-kHz Oscillator
      4. 3.7.4  External Memory Interface A (ASYNC, SDRAM)
      5. 3.7.5  External Memory Interface B (only SDRAM)
      6. 3.7.6  Serial Peripheral Interface Modules (SPI0, SPI1)
      7. 3.7.7  Enhanced Capture/Auxiliary PWM Modules (eCAP0, eCAP1, eCAP2)
      8. 3.7.8  Enhanced Pulse Width Modulators (eHRPWM0, eHRPWM1, eHRPWM2)
      9. 3.7.9  Enhanced Quadrature Encoder Pulse Module (eQEP)
      10. 3.7.10 Boot
      11. 3.7.11 Universal Asynchronous Receiver/Transmitters (UART0, UART1, UART2)
      12. 3.7.12 Inter-Integrated Circuit Modules(I2C0, I2C1)
      13. 3.7.13 Timers
      14. 3.7.14 Universal Host-Port Interface (UHPI)
      15. 3.7.15 Multichannel Audio Serial Ports (McASP0, McASP1, McASP2)
      16. 3.7.16 Universal Serial Bus Modules (USB0, USB1)
      17. 3.7.17 Ethernet Media Access Controller (EMAC)
      18. 3.7.18 Multimedia Card/Secure Digital (MMC/SD)
      19. 3.7.19 Liquid Crystal Display Controller (LCD)
      20. 3.7.20 Reserved and No Connect
      21. 3.7.21 Supply and Ground
      22. 3.7.22 Unused USB0 (USB2.0) and USB1 (USB1.1) Pin Configurations
  4. 4Device Configuration
    1. 4.1 Boot Modes
    2. 4.2 SYSCFG Module
    3. 4.3 Pullup/Pulldown Resistors
    4. 4.4 Absolute Maximum Ratings Over Operating Case Temperature Range (Unless Otherwise Noted)
    5. 4.5 Handling Ratings
    6. 4.6 Recommended Operating Conditions
    7. 4.7 Notes on Recommended Power-On Hours (POH)
    8. 4.8 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Case Temperature (Unless Otherwise Noted)
  5. 5Peripheral Information and Electrical Specifications
    1. 5.1  Parameter Information
      1. 5.1.1 Parameter Information Device-Specific Information
        1. 5.1.1.1 Signal Transition Levels
    2. 5.2  Recommended Clock and Control Signal Transition Behavior
    3. 5.3  Power Supplies
      1. 5.3.1 Power-on Sequence
      2. 5.3.2 Power-off Sequence
    4. 5.4  Reset
      1. 5.4.1 Power-On Reset (POR)
      2. 5.4.2 Warm Reset
      3. 5.4.3 Reset Electrical Data Timings
    5. 5.5  Crystal Oscillator or External Clock Input
    6. 5.6  Clock PLLs
      1. 5.6.1 PLL Device-Specific Information
      2. 5.6.2 Device Clock Generation
      3. 5.6.3 PLL Controller 0 Registers
    7. 5.7  Interrupts
      1. 5.7.1 ARM CPU Interrupts
        1. 5.7.1.1 ARM Interrupt Controller (AINTC) Interrupt Signal Hierarchy
        2. 5.7.1.2 AINTC Hardware Vector Generation
        3. 5.7.1.3 AINTC Hardware Interrupt Nesting Support
        4. 5.7.1.4 AINTC System Interrupt Assignments on OMAP-L137
        5. 5.7.1.5 AINTC Memory Map
      2. 5.7.2 DSP Interrupts
      3. 5.7.3 ARM/DSP Communications Interrupts
    8. 5.8  General-Purpose Input/Output (GPIO)
      1. 5.8.1 GPIO Register Description(s)
      2. 5.8.2 GPIO Peripheral Input/Output Electrical Data/Timing
      3. 5.8.3 GPIO Peripheral External Interrupts Electrical Data/Timing
    9. 5.9  EDMA
    10. 5.10 External Memory Interface A (EMIFA)
      1. 5.10.1 EMIFA Asynchronous Memory Support
      2. 5.10.2 EMIFA Synchronous DRAM Memory Support
      3. 5.10.3 EMIFA SDRAM Loading Limitations
      4. 5.10.4 EMIFA Connection Examples
      5. 5.10.5 External Memory Interface A (EMIFA) Registers
      6. 5.10.6 EMIFA Electrical Data/Timing
    11. 5.11 External Memory Interface B (EMIFB)
      1. 5.11.1 EMIFB SDRAM Loading Limitations
      2. 5.11.2 Interfacing to SDRAM
      3. 5.11.3 EMIFB Electrical Data/Timing
    12. 5.12 Memory Protection Units
    13. 5.13 MMC / SD / SDIO (MMCSD)
      1. 5.13.1 MMCSD Peripheral Description
      2. 5.13.2 MMCSD Peripheral Register Description(s)
      3. 5.13.3 MMC/SD Electrical Data/Timing
    14. 5.14 Ethernet Media Access Controller (EMAC)
      1. 5.14.1 EMAC Peripheral Register Description(s)
    15. 5.15 Management Data Input/Output (MDIO)
      1. 5.15.1 MDIO Registers
      2. 5.15.2 Management Data Input/Output (MDIO) Electrical Data/Timing
    16. 5.16 Multichannel Audio Serial Ports (McASP0, McASP1, and McASP2)
      1. 5.16.1 McASP Peripheral Registers Description(s)
      2. 5.16.2 McASP Electrical Data/Timing
        1. 5.16.2.1 Multichannel Audio Serial Port 0 (McASP0) Timing
        2. 5.16.2.2 Multichannel Audio Serial Port 1 (McASP1) Timing
        3. 5.16.2.3 Multichannel Audio Serial Port 2 (McASP2) Timing
    17. 5.17 Serial Peripheral Interface Ports (SPI0, SPI1)
      1. 5.17.1 SPI Peripheral Registers Description(s)
      2. 5.17.2 SPI Electrical Data/Timing
        1. 5.17.2.1 Serial Peripheral Interface (SPI) Timing
    18. 5.18 Enhanced Capture (eCAP) Peripheral
    19. 5.19 Enhanced Quadrature Encoder (eQEP) Peripheral
    20. 5.20 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM)
      1. 5.20.1 Enhanced Pulse Width Modulator (eHRPWM) Timing
      2. 5.20.2 Trip-Zone Input Timing
    21. 5.21 LCD Controller
      1. 5.21.1 LCD Interface Display Driver (LIDD Mode)
      2. 5.21.2 LCD Raster Mode
    22. 5.22 Timers
      1. 5.22.1 Timer Electrical Data/Timing
    23. 5.23 Inter-Integrated Circuit Serial Ports (I2C0, I2C1)
      1. 5.23.1 I2C Device-Specific Information
      2. 5.23.2 I2C Peripheral Registers Description(s)
      3. 5.23.3 I2C Electrical Data/Timing
        1. 5.23.3.1 Inter-Integrated Circuit (I2C) Timing
    24. 5.24 Universal Asynchronous Receiver/Transmitter (UART)
      1. 5.24.1 UART Peripheral Registers Description(s)
      2. 5.24.2 UART Electrical Data/Timing
    25. 5.25 USB1 Host Controller Registers (USB1.1 OHCI)
      1. 5.25.1 USB1 Unused Signal Configuration
    26. 5.26 USB0 OTG (USB2.0 OTG)
      1. 5.26.1 USB2.0 Electrical Data/Timing
      2. 5.26.2 USB0 Unused Signal Configuration
    27. 5.27 Host-Port Interface (UHPI)
      1. 5.27.1 HPI Device-Specific Information
      2. 5.27.2 HPI Peripheral Register Description(s)
      3. 5.27.3 HPI Electrical Data/Timing
    28. 5.28 Power and Sleep Controller (PSC)
      1. 5.28.1 Power Domain and Module Topology
        1. 5.28.1.1 Power Domain States
        2. 5.28.1.2 Module States
    29. 5.29 Programmable Real-Time Unit Subsystem (PRUSS)
      1. 5.29.1 PRUSS Register Descriptions
    30. 5.30 Emulation Logic
      1. 5.30.1 JTAG Port Description
      2. 5.30.2 Scan Chain Configuration Parameters
      3. 5.30.3 Initial Scan Chain Configuration
        1. 5.30.3.1 Adding TAPS to the Scan Chain
      4. 5.30.4 JTAG 1149.1 Boundary Scan Considerations
    31. 5.31 IEEE 1149.1 JTAG
      1. 5.31.1 JTAG Peripheral Register Description(s) - JTAG ID Register (DEVIDR0)
      2. 5.31.2 JTAG Test-Port Electrical Data/Timing
    32. 5.32 Real Time Clock (RTC)
      1. 5.32.1 Clock Source
      2. 5.32.2 Real-Time Clock Registers
  6. 6Device and Documentation Support
    1. 6.1 Device Support
      1. 6.1.1 Development Support
      2. 6.1.2 Device and Development-Support Tool Nomenclature
    2. 6.2 Documentation Support
    3. 6.3 Community Resources
    4. 6.4 Trademarks
    5. 6.5 Electrostatic Discharge Caution
    6. 6.6 Glossary
  7. 7Mechanical Packaging and Orderable Information
    1. 7.1 Thermal Data for ZKB
    2. 7.2 Packaging Information

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2 Revision History

This data manual revision history highlights the changes made to the SPRS563F device-specific data manual to make it an SPRS563G revision.

Scope: Applicable updates to the OMAP-L137 Low-Power Applications Processor device family, specifically relating to the OMAP-L137 device, which are all now in the production data (PD) stage of development, have been incorporated.

    Revision History

    SEE ADDITIONS/MODIFICATIONS/DELETIONS
    Global
    • Turned on Navigation Icons on top of first page.
    • Updated Features, Applications, and Description for consistency and translation.
    • Moved Trademarks information from first page to within Section 6, Device and Documentation Support.
    • Moved ESDS Warning to within Section 6, Device and Documentation Support.
    Section 1.1
    Features    		 Deleted Highlights section. Information was duplicated elsewhere in Features.
    Section 1.2
    Applications    		 Added NEW section.
    Section 1.3
    Description    		 Added NEW Device Information Table.
    Section 3.4.2.4
    C674x CPU    		 Table 3-2, C674x Cache Registers:
    • Updated/Changed REGISTER DESCRIPTION for BYTE ADDRESSES 0000, 0020, and 0040 from "...See the System reference Guide..." to "See the Technical Reference Manual..."
    Section 3.7
    Terminal Functions    		 Table 3-20, Universal Serial Bus (USB) Terminal Functions:
    • Updated/Changed USB0_VDDA12 DESCRIPTION from "...must always be connected via a 1 μF capacitor..." to "...is recommended to be connected via a 0.22-μF capacitor..."
    Section 3.7.11
    Universal Asynchronous Receiver/Transmitters (UART0, UART1, UART2)    		 Table 3-15, Universal Asynchronous Receiver/Transmitter (UART) Terminal Functions:
    • Updated/Changed footnote from "...Applications Processor System Reference Guide - Literature Number SPRUG84..." to "...C6000 DSP+ARM Processor Technical Reference Manual (SPRUH92)..."
    Section 3.7.22
    Unused USB0 (USB2.0) and USB1 (USB1.1) Pin Configurations    		 Moved to within Section 3.7, Terminal Functions
    Table 3-26, Unused USB0 and USB1 Pin Configurations:
    • Updated/Changed USB0_VDDA12 Configuration by combining both Configuration columns and changing text to "Internal USB0 PHY output connected to an external..."

    Device Operating Conditions    		 Section 4.5, Handling Ratings:
    • Split handling, ratings, and certifications from the Abs Max table and placed in NEW Handling Ratings table.
    Section 4.7
    Notes on Recommended Power-On Hours (POH)    		 Table 4-1, Recommended Power-On Hours:
    • Added Silicon Revision column.
    Section 5.10.6
    EMIFA Electrical Data/Timing    		 Table 5-24, EMIFA Asynchronous Memory Switching Characteristics:
    • Updated/Changed the MIN, NOM, and MAX equations for NO. 3, 10, 15, and 24 from "...(EWC*16)..." to "...EWC..."
    Section 4.6, Recommended Operating Conditions:
    • Added "Unless specifically indicated" to "These I/O specifications apply to ..." footnote
    Section 5.11.3
    EMIFB Electrical Data/Timing    		 Table 5-28, EMIFB SDRAM Interface Timing Requirements:
    • Updated/Changed Parameter No. 19 from "tsu(DV-CLKH)" to "t(DV-CLKH)"
    • Added new column: "CVDD = 1.3V"
    • Added new footnote containing "...range rated devices for 456 MHz max CPU operating..."
    • Added new footnote containing "...range rated devices for 400/375/300/266/200 MHz max CPU operating ..."
    Table 5-29, EMIFB SDRAM Interface Switching Characteristics for Commercial (Default) Temperature Range:
    • Updated/Changed table title from "...Switching Characteristics..." to "...Switching Characteristics for Commercial (Default) Temperature Range"
    • Added new footnote containing "...range rated devices for 456 MHz max CPU operating ..."
    • Added new footnote containing "...range rated devices for 400/375/300/266/200 MHz max CPU operating..."
    • Updated/Changed CVDD = 1.3V MIN column values for Parameter No. 4, 6, 8, 10, 12, 14, 16, and 18 from "0.9" to "1.1"
    • Updated/Changed CVDD = 1.3V MAX column values for Parameter No. 3, 5, 7, 9, 11, 13, 15, and 17 from "5.1" to "4.25"
    • Populated CVDD = 1.2V column with values (was empty)
    • Updated/Changed Parameter No. 18 from "tena(CLKH-DLZ)" to "t(CLKH-DLZ)"
    Table 5-30, EMIFB SDRAM Interface Switching Characteristics for Industrial, Extended, and Automotive Temperature Ranges:
    • Added NEW table
    Section 5.16
    Multichannel Audio Serial Ports (McASP0, McASP1, and McASP2)    		 Table 5-47, McASP Registers Accessed Through DMA Port:
    • Updated/Changed Read Accesses Register Description from "XBUSEL = 0 in XFMT" to "RBUSEL = 0 in RFMT"
    • Updated/Changed Write Accesses Register Description from "RBUSEL = 0 in RFMT" to "XBUSEL = 0 in XFMT"
    Section 6.6
    Glossary    		 Added NEW section.