ZHCS180L July   2011  – December 2017 MSP430FR5730 , MSP430FR5731 , MSP430FR5732 , MSP430FR5733 , MSP430FR5734 , MSP430FR5735 , MSP430FR5736 , MSP430FR5737 , MSP430FR5738 , MSP430FR5739

PRODUCTION DATA.  

  1. 1器件概述
    1. 1.1 特性
    2. 1.2 应用范围
    3.     4
    4. 1.3 说明
    5. 1.4 功能方框图
  2. 2修订历史记录
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagram – RHA Package – MSP430FR5731, MSP430FR5733, MSP430FR5735, MSP430FR5737, MSP430FR5739
    2. 4.2 Pin Diagram – DA Package – MSP430FR5731, MSP430FR5733, MSP430FR5735, MSP430FR5737, MSP430FR5739
    3. 4.3 Pin Diagram – RGE Package – MSP430FR5730, MSP430FR5732, MSP430FR5734, MSP430FR5736, MSP430FR5738
    4. 4.4 Pin Diagram – YQD Package – MSP430FR5738
    5. 4.5 Pin Diagram – PW Package – MSP430FR5730, MSP430FR5732, MSP430FR5734, MSP430FR5736, MSP430FR5738
    6. 4.6 Signal Descriptions
      1. Table 4-1 Signal Descriptions
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 5.5  Low-Power Mode Supply Currents (Into VCC) Excluding External Current
    6. 5.6  Thermal Resistance Characteristics
    7. 5.7  Schmitt-Trigger Inputs – General-Purpose I/O (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.1, PJ.0 to PJ.5, RST/NMI)
    8. 5.8  Inputs – Ports P1 and P2 (P1.0 to P1.7, P2.0 to P2.7)
    9. 5.9  Leakage Current – General-Purpose I/O (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.1, PJ.0 to PJ.5, RST/NMI)
    10. 5.10 Outputs – General-Purpose I/O (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.1, PJ.0 to PJ.5)
    11. 5.11 Output Frequency – General-Purpose I/O (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.1, PJ.0 to PJ.5)
    12. 5.12 Typical Characteristics – Outputs
    13. 5.13 Crystal Oscillator, XT1, Low-Frequency (LF) Mode
    14. 5.14 Crystal Oscillator, XT1, High-Frequency (HF) Mode
    15. 5.15 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
    16. 5.16 DCO Frequencies
    17. 5.17 MODOSC
    18. 5.18 PMM, Core Voltage
    19. 5.19 PMM, SVS, BOR
    20. 5.20 Wake-up Times From Low-Power Modes
    21. 5.21 Timer_A
    22. 5.22 Timer_B
    23. 5.23 eUSCI (UART Mode) Clock Frequency
    24. 5.24 eUSCI (UART Mode)
    25. 5.25 eUSCI (SPI Master Mode) Clock Frequency
    26. 5.26 eUSCI (SPI Master Mode)
    27. 5.27 eUSCI (SPI Slave Mode)
    28. 5.28 eUSCI (I2C Mode)
    29. 5.29 10-Bit ADC, Power Supply and Input Range Conditions
    30. 5.30 10-Bit ADC, Timing Parameters
    31. 5.31 10-Bit ADC, Linearity Parameters
    32. 5.32 REF, External Reference
    33. 5.33 REF, Built-In Reference
    34. 5.34 REF, Temperature Sensor and Built-In VMID
    35. 5.35 Comparator_D
    36. 5.36 FRAM
    37. 5.37 JTAG and Spy-Bi-Wire Interface
  6. 6Detailed Description
    1. 6.1  Functional Block Diagrams
    2. 6.2  CPU
    3. 6.3  Operating Modes
    4. 6.4  Interrupt Vector Addresses
    5. 6.5  Memory Organization
    6. 6.6  Bootloader (BSL)
    7. 6.7  JTAG Operation
      1. 6.7.1 JTAG Standard Interface
      2. 6.7.2 Spy-Bi-Wire Interface
    8. 6.8  FRAM
    9. 6.9  Memory Protection Unit (MPU)
    10. 6.10 Peripherals
      1. 6.10.1  Digital I/O
      2. 6.10.2  Oscillator and Clock System (CS)
      3. 6.10.3  Power-Management Module (PMM)
      4. 6.10.4  Hardware Multiplier (MPY)
      5. 6.10.5  Real-Time Clock (RTC_B)
      6. 6.10.6  Watchdog Timer (WDT_A)
      7. 6.10.7  System Module (SYS)
      8. 6.10.8  DMA Controller
      9. 6.10.9  Enhanced Universal Serial Communication Interface (eUSCI)
      10. 6.10.10 TA0, TA1
      11. 6.10.11 TB0, TB1, TB2
      12. 6.10.12 ADC10_B
      13. 6.10.13 Comparator_D
      14. 6.10.14 CRC16
      15. 6.10.15 Shared Reference (REF)
      16. 6.10.16 Embedded Emulation Module (EEM)
      17. 6.10.17 Peripheral File Map
    11. 6.11 Input/Output Diagrams
      1. 6.11.1  Port P1 (P1.0 to P1.2) Input/Output With Schmitt Trigger
      2. 6.11.2  Port P1 (P1.3 to P1.5) Input/Output With Schmitt Trigger
      3. 6.11.3  Port P1 (P1.6 and P1.7) Input/Output With Schmitt Trigger
      4. 6.11.4  Port P2 (P2.0 to P2.2) Input/Output With Schmitt Trigger
      5. 6.11.5  Port P2 (P2.3 and P2.4) Input/Output With Schmitt Trigger
      6. 6.11.6  Port P2 (P2.5 and P2.6) Input/Output With Schmitt Trigger
      7. 6.11.7  Port P2 (P2.7) Input/Output With Schmitt Trigger
      8. 6.11.8  Port P3 (P3.0 to P3.3) Input/Output With Schmitt Trigger
      9. 6.11.9  Port P3 (P3.4 to P3.6) Input/Output With Schmitt Trigger
      10. 6.11.10 Port Port P3 (P3.7) Input/Output With Schmitt Trigger
      11. 6.11.11 Port Port P4 (P4.0) Input/Output With Schmitt Trigger
      12. 6.11.12 Port Port P4 (P4.1) Input/Output With Schmitt Trigger
      13. 6.11.13 Port Port PJ (PJ.0 to PJ.3) JTAG Pins TDO, TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output
      14. 6.11.14 Port Port PJ (PJ.4 and PJ.5) Input/Output With Schmitt Trigger
    12. 6.12 Device Descriptors (TLV)
  7. 7器件和文档支持
    1. 7.1  开始使用
    2. 7.2  Device Nomenclature
    3. 7.3  工具和软件
    4. 7.4  文档支持
    5. 7.5  相关链接
    6. 7.6  社区资源
    7. 7.7  商标
    8. 7.8  静电放电警告
    9. 7.9  出口管制提示
    10. 7.10 术语表
  8. 8机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

3 Device Comparison

Table 3-1 summarizes the available family members.

Table 3-1 Family Members(3)(4)

DEVICEFRAM
(KB)		SRAM
(KB)		SYSTEM CLOCK
(MHz)		ADC10_BComp_DTimer_A(1)Timer_B(2)eUSCI I/OPACKAGE
Channel A:
UART, IrDA, SPI		Channel B:
SPI, I2C
MSP430FR5739 16 1 24 12 ext, 2 int ch. 16 ch. 3, 3 3, 3, 3 2 1 32 RHA
30 DA
MSP430FR5738 16 1 24 6 ext, 2 int ch. 10 ch. 3, 3 3 1 1 17 RGE
8 ext, 2 int ch. 12 ch. 21 PW
6 ext, 2 int ch. 10 ch. 17 YQD
MSP430FR5737 16 1 24 – 16 ch. 3, 3 3, 3, 3 2 1 32 RHA
30 DA
MSP430FR5736 16 1 24 – 10 ch. 3, 3 3 1 1 17 RGE
12 ch. 21 PW
MSP430FR5735 8 1 24 12 ext, 2 int ch. 16 ch. 3, 3 3, 3, 3 2 1 32 RHA
30 DA
MSP430FR5734 8 1 24 6 ext, 2 int ch. 10 ch. 3, 3 3 1 1 17 RGE
8 ext, 2 int ch. 12 ch. 21 PW
MSP430FR5733 8 1 24 – 16 ch. 3, 3 3, 3, 3 2 1 32 RHA
30 DA
MSP430FR5732 8 1 24 – 10 ch. 3, 3 3 1 1 17 RGE
12 ch. 21 PW
MSP430FR5731 4 1 24 12 ext, 2 int ch. 16 ch. 3, 3 3, 3, 3 2 1 32 RHA
30 DA
MSP430FR5730 4 1 24 6 ext, 2 int ch. 10 ch. 3, 3 3 1 1 17 RGE
8 ext, 2 int ch. 12 ch. 21 PW
(1) Each number in the sequence represents an instantiation of Timer_A with its associated number of capture/compare registers and PWM output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_A, the first instantiation having 3 and the second instantiation having 5 capture/compare registers and PWM output generators, respectively.
(2) Each number in the sequence represents an instantiation of Timer_B with its associated number of capture/compare registers and PWM output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_B, the first instantiation having 3 and the second instantiation having 5 capture/compare registers and PWM output generators, respectively.
(3) For the most current package and ordering information, see the Package Option Addendum in Section 8, or see the TI website at www.ti.com.
(4) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/packaging.