ZHCS409G June   2010  – September 2020 MSP430F6630 , MSP430F6631 , MSP430F6632 , MSP430F6633 , MSP430F6634 , MSP430F6635 , MSP430F6636 , MSP430F6637 , MSP430F6638

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 功能方框图
  5. 5 Revision History
  6. 6 Device Comparison
    1. 6.1 Related Products
  7. 7 Terminal Configuration and Functions
    1. 7.1 Pin Diagrams
    2. 7.2 Signal Descriptions
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 8.5  Low-Power Mode Supply Currents (Into VCC) Excluding External Current
    6. 8.6  Low-Power Mode With LCD Supply Currents (Into VCC) Excluding External Current
    7. 8.7  Thermal Resistance Characteristics
    8. 8.8  Schmitt-Trigger Inputs – General-Purpose I/O
    9. 8.9  Inputs – Ports P1, P2, P3, and P4
    10. 8.10 Leakage Current – General-Purpose I/O
    11. 8.11 Outputs – General-Purpose I/O (Full Drive Strength)
    12. 8.12 Outputs – General-Purpose I/O (Reduced Drive Strength)
    13. 8.13 Output Frequency – Ports P1, P2, and P3
    14. 8.14 Typical Characteristics – Outputs, Reduced Drive Strength (PxDS.y = 0)
    15. 8.15 Typical Characteristics – Outputs, Full Drive Strength (PxDS.y = 1)
    16. 8.16 Crystal Oscillator, XT1, Low-Frequency Mode
    17. 8.17 Crystal Oscillator, XT2
    18. 8.18 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
    19. 8.19 Internal Reference, Low-Frequency Oscillator (REFO)
    20. 8.20 DCO Frequency
    21. 8.21 PMM, Brownout Reset (BOR)
    22. 8.22 PMM, Core Voltage
    23. 8.23 PMM, SVS High Side
    24. 8.24 PMM, SVM High Side
    25. 8.25 PMM, SVS Low Side
    26. 8.26 PMM, SVM Low Side
    27. 8.27 Wake-up Times From Low-Power Modes and Reset
    28. 8.28 Timer_A, Timers TA0, TA1, and TA2
    29. 8.29 Timer_B, Timer TB0
    30. 8.30 Battery Backup
    31. 8.31 USCI (UART Mode)
    32. 8.32 USCI (SPI Master Mode)
    33. 8.33 USCI (SPI Slave Mode)
    34. 8.34 USCI (I2C Mode)
    35. 8.35 LCD_B, Recommended Operating Conditions
    36. 8.36 LCD_B, Electrical Characteristics
    37. 8.37 12-Bit ADC, Power Supply and Input Range Conditions
    38. 8.38 12-Bit ADC, Timing Parameters
    39. 8.39 12-Bit ADC, Linearity Parameters Using an External Reference Voltage
    40. 8.40 12-Bit ADC, Linearity Parameters Using AVCC as Reference Voltage
    41. 8.41 12-Bit ADC, Linearity Parameters Using the Internal Reference Voltage
    42. 8.42 12-Bit ADC, Temperature Sensor and Built-In VMID
    43. 8.43 REF, External Reference
    44. 8.44 REF, Built-In Reference
    45. 8.45 12-Bit DAC, Supply Specifications
    46. 8.46 12-Bit DAC, Linearity Specifications
    47. 8.47 12-Bit DAC, Output Specifications
    48. 8.48 12-Bit DAC, Reference Input Specifications
    49. 8.49 12-Bit DAC, Dynamic Specifications
    50. 8.50 12-Bit DAC, Dynamic Specifications (Continued)
    51. 8.51 Comparator_B
    52. 8.52 Ports PU.0 and PU.1
    53. 8.53 USB Output Ports DP and DM
    54. 8.54 USB Input Ports DP and DM
    55. 8.55 USB-PWR (USB Power System)
    56. 8.56 USB-PLL (USB Phase-Locked Loop)
    57. 8.57 Flash Memory
    58. 8.58 JTAG and Spy-Bi-Wire Interface
  9. 9 Detailed Description
    1. 9.1  Overview
    2. 9.2  CPU
    3. 9.3  Instruction Set
    4. 9.4  Operating Modes
    5. 9.5  Interrupt Vector Addresses
    6. 9.6  Memory
    7. 9.7  Bootloader (BSL)
      1. 9.7.1 USB BSL
      2. 9.7.2 UART BSL
    8. 9.8  JTAG Operation
      1. 9.8.1 JTAG Standard Interface
      2. 9.8.2 Spy-Bi-Wire Interface
    9. 9.9  Flash Memory
    10. 9.10 RAM
    11. 9.11 Backup RAM
    12. 9.12 Peripherals
      1. 9.12.1  Digital I/O
      2. 9.12.2  Port Mapping Controller
      3. 9.12.3  Oscillator and System Clock
      4. 9.12.4  Power-Management Module (PMM)
      5. 9.12.5  Hardware Multiplier (MPY) (Link to User's Guide)
      6. 9.12.6  Real-Time Clock (RTC_B)
      7. 9.12.7  Watchdog Timer (WDT_A)
      8. 9.12.8  System Module (SYS)
      9. 9.12.9  DMA Controller
      10. 9.12.10 Universal Serial Communication Interface (USCI)
      11. 9.12.11 Timer TA0
      12. 9.12.12 Timer TA1
      13. 9.12.13 Timer TA2
      14. 9.12.14 Timer TB0
      15. 9.12.15 Comparator_B
      16. 9.12.16 ADC12_A
      17. 9.12.17 DAC12_A
      18. 9.12.18 CRC16
      19. 9.12.19 Voltage Reference (REF) Module
      20. 9.12.20 LCD_B
      21. 9.12.21 USB Universal Serial Bus
      22. 9.12.22 Embedded Emulation Module (EEM)
      23. 9.12.23 Peripheral File Map
    13. 9.13 Input/Output Diagrams
      1. 9.13.1  Port P1 (P1.0 to P1.7) Input/Output With Schmitt Trigger
      2. 9.13.2  Port P2 (P2.0 to P2.7) Input/Output With Schmitt Trigger
      3. 9.13.3  Port P3 (P3.0 to P3.7) Input/Output With Schmitt Trigger
      4. 9.13.4  Port P4 (P4.0 to P4.7) Input/Output With Schmitt Trigger
      5. 9.13.5  Port P5 (P5.0 and P5.1) Input/Output With Schmitt Trigger
      6. 9.13.6  Port P5 (P5.2 to P5.7) Input/Output With Schmitt Trigger
      7. 9.13.7  Port P6 (P6.0 to P6.7) Input/Output With Schmitt Trigger
      8. 9.13.8  Port P7 (P7.2) Input/Output With Schmitt Trigger
      9. 9.13.9  Port P7 (P7.3) Input/Output With Schmitt Trigger
      10. 9.13.10 Port P7 (P7.4 to P7.7) Input/Output With Schmitt Trigger
      11. 9.13.11 Port P8 (P8.0 to P8.7) Input/Output With Schmitt Trigger
      12. 9.13.12 Port P9 (P9.0 to P9.7) Input/Output With Schmitt Trigger
      13. 9.13.13 Port PU (PU.0/DP, PU.1/DM, PUR) USB Ports
      14. 9.13.14 Port PJ (PJ.0) JTAG Pin TDO, Input/Output With Schmitt Trigger or Output
      15. 9.13.15 Port PJ (PJ.1 to PJ.3) JTAG Pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output
    14. 9.14 Device Descriptors
  10. 10Device and Documentation Support
    1. 10.1  Getting Started and Next Steps
    2. 10.2  Device Nomenclature
    3. 10.3  Tools and Software
    4. 10.4  Documentation Support
    5. 10.5  Related Links
    6. 10.6  支持资源
    7. 10.7  Trademarks
    8. 10.8  静电放电警告
    9. 10.9  Export Control Notice
    10. 10.10 术语表
  11. 11Mechanical, Packaging, and Orderable Information

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9.5 Interrupt Vector Addresses

The interrupt vectors and the power-up start address are in the address range 0FFFFh to 0FF80h (see Table 9-3). The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.

Table 9-3 Interrupt Sources, Flags, and Vectors of MSP430F663x Configurations
INTERRUPT SOURCE INTERRUPT FLAG SYSTEM INTERRUPT WORD ADDRESS PRIORITY
System Reset
Power-Up, External Reset
Watchdog Time-out, Key Violation
Flash Memory Key Violation
 WDTIFG, KEYV (SYSRSTIV)(1)(3) Reset 0FFFEh 63, highest
System NMI
PMM
Vacant Memory Access
JTAG Mailbox		 SVMLIFG, SVMHIFG, DLYLIFG, DLYHIFG, VLRLIFG, VLRHIFG, VMAIFG, JMBNIFG, JMBOUTIFG (SYSSNIV)(1) (Non)maskable 0FFFCh 62
User NMI
NMI
Oscillator Fault
Flash Memory Access Violation		 NMIIFG, OFIFG, ACCVIFG, BUSIFG (SYSUNIV)(1)(3) (Non)maskable 0FFFAh 61
Comp_B Comparator B interrupt flags (CBIV)(1)(2) Maskable 0FFF8h 60
Timer TB0 TB0CCR0 CCIFG0(2) Maskable 0FFF6h 59
Timer TB0 TB0CCR1 CCIFG1 to TB0CCR6 CCIFG6,
TB0IFG (TBIV)(1) (2)		 Maskable 0FFF4h 58
Watchdog Interval Timer Mode WDTIFG Maskable 0FFF2h 57
USCI_A0 Receive or Transmit UCA0RXIFG, UCA0TXIFG (UCA0IV)(1)(2) Maskable 0FFF0h 56
USCI_B0 Receive or Transmit UCB0RXIFG, UCB0TXIFG (UCB0IV)(1)(2) Maskable 0FFEEh 55
ADC12_A(5) ADC12IFG0 to ADC12IFG15 (ADC12IV)(1)(2) Maskable 0FFECh 54
Timer TA0 TA0CCR0 CCIFG0(2) Maskable 0FFEAh 53
Timer TA0 TA0CCR1 CCIFG1 to TA0CCR4 CCIFG4,
TA0IFG (TA0IV)(1)(2)		 Maskable 0FFE8h 52
USB_UBM USB interrupts (USBIV)(1)(2) Maskable 0FFE6h 51
DMA DMA0IFG, DMA1IFG, DMA2IFG, DMA3IFG, DMA4IFG, DMA5IFG (DMAIV)(1)(2) Maskable 0FFE4h 50
Timer TA1 TA1CCR0 CCIFG0(2) Maskable 0FFE2h 49
Timer TA1 TA1CCR1 CCIFG1 to TA1CCR2 CCIFG2,
TA1IFG (TA1IV)(1)(2)		 Maskable 0FFE0h 48
I/O Port P1 P1IFG.0 to P1IFG.7 (P1IV)(1) (2) Maskable 0FFDEh 47
USCI_A1 Receive or Transmit UCA1RXIFG, UCA1TXIFG (UCA1IV)(1)(2) Maskable 0FFDCh 46
USCI_B1 Receive or Transmit UCB1RXIFG, UCB1TXIFG (UCB1IV)(1)(2) Maskable 0FFDAh 45
I/O Port P2 P2IFG.0 to P2IFG.7 (P2IV)(1) (2) Maskable 0FFD8h 44
LCD_B LCD_B Interrupt Flags (LCDBIV)(1) Maskable 0FFD6h 43
RTC_B RTCRDYIFG, RTCTEVIFG, RTCAIFG, RT0PSIFG, RT1PSIFG, RTCOFIFG (RTCIV)(1)(2) Maskable 0FFD4h 42
DAC12_A(6) DAC12_0IFG, DAC12_1IFG(1)(2) Maskable 0FFD2h 41
Timer TA2 TA2CCR0 CCIFG0(2) Maskable 0FFD0h 40
Timer TA2 TA2CCR1 CCIFG1 to TA2CCR2 CCIFG2,
TA2IFG (TA2IV)(1)(2)		 Maskable 0FFCEh 39
I/O Port P3 P3IFG.0 to P3IFG.7 (P3IV)(1)(2) Maskable 0FFCCh 38
I/O Port P4 P4IFG.0 to P4IFG.7 (P4IV)(1)(2) Maskable 0FFCAh 37
Reserved Reserved(4) 0FFC8h 36
⋮ ⋮
0FF80h 0, lowest
(1) Multiple source flags
(2) Interrupt flags are in the module.
(3) A reset is generated if the CPU tries to fetch instructions from within peripheral space or vacant memory space.
(Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot disable it.
(4) Reserved interrupt vectors at addresses are not used in this device and can be used for regular program code if necessary. To maintain compatibility with other devices, TI recommends reserving these locations.
(5) Only on devices with peripheral module ADC12_A, otherwise reserved.
(6) Only on devices with peripheral module DAC12_A, otherwise reserved.