ZHCSFP8C December   2015  – September 2016 LP5912-Q1

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Voltage Options
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Output and Input Capacitors
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Enable (EN)
      2. 8.3.2 Output Automatic Discharge (RAD)
      3. 8.3.3 Reverse Current Protection (IRO)
      4. 8.3.4 Internal Current Limit (ISC)
      5. 8.3.5 Thermal Overload Protection (TSD)
      6. 8.3.6 Power-Good Output (PG)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Enable (EN)
      2. 8.4.2 Minimum Operating Input Voltage (VIN)
  9. 9 Applications and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 External Capacitors
        2. 9.2.2.2 Input Capacitor
        3. 9.2.2.3 Output Capacitor
        4. 9.2.2.4 Capacitor Characteristics
        5. 9.2.2.5 Remote Capacitor Operation
        6. 9.2.2.6 Power Dissipation
        7. 9.2.2.7 Estimating Junction Temperature
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 相关文档　
    2. 12.2 接收文档更新通知
    3. 12.3 社区资源
    4. 12.4 商标
    5. 12.5 静电放电警告
    6. 12.6 Glossary
  13. 13机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

11 Layout

11.1 Layout Guidelines

The dynamic performance of the LP5912-Q1 is dependant on the layout of the PCB. PCB layout practices that are adequate for typical LDOs may degrade the PSRR, noise, or transient performance of the LP5912-Q1.

Best performance is achieved by placing CIN and COUT on the same side of the PCB as the LP5912-Q1, and as close to the package as is practical. The ground connections for CIN and COUT must be back to the LP5912-Q1 ground pin using as wide and as short of a copper trace as is practical.

Connections using long trace lengths, narrow trace widths, or connections through vias must be avoided. Such connections add parasitic inductances and resistance that result in inferior performance especially during transient conditions.

11.2 Layout Example

LP5912-Q1 layout_snvsa77.gif Figure 57. LP5912-Q1 Typical Layout