ZHCSOW8 July 2022 LP5912-EP
PRODUCTION DATA
To ensure stability, the LP5912-EP requires at least a 1-μF capacitor at the OUT pin. There is no strict requirement for the location of the output capacitor in regards to the LDO OUT pin; the output capacitor can be located 5 cm to 10 cm away from the LDO. This flexibility means that there is no need to have a special capacitor close to the OUT pin if there are already respective capacitors in the system. This placement flexibility requires that the output capacitor be connected directly between the LP5912-EP OUT pin and GND pin with no vias. This remote capacitor feature can help designers minimize the number of capacitors in the system.
As a good design practice, keep the wiring parasitic inductance at a minimum. Thus, use traces that are as wide as possible from the LDO output to the capacitors, keeping the LDO output trace layer as close to ground layer as possible and avoiding vias on the path. If there is a need to use vias, implement as many vias as possible between the connection layers. Keep parasitic wiring inductance less than 35 nH. For applications with fast load transients, use an input capacitor equal to (or larger than) the sum of the capacitance at the output node for the best load-transient performance.