ZHCSOR5 January   2022 LP5861

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Analog Dimming (Current Gain Control)
      2. 8.3.2 PWM Dimming
      3. 8.3.3 ON and OFF Control
      4. 8.3.4 Data Refresh Mode
      5. 8.3.5 Full Addressable SRAM
      6. 8.3.6 Protections and Diagnostics
    4. 8.4 Device Functional Modes
    5. 8.5 Programming
    6. 8.6 Register Maps
      1. 8.6.1 CONFIG Registers
      2. 8.6.2 GROUP Registers
      3. 8.6.3 DOTGROUP Registers
      4. 8.6.4 DOTONOFF Registers
      5. 8.6.5 FAULT Registers
      6. 8.6.6 RESET Registers
      7. 8.6.7 DC Registers
      8. 8.6.8 PWM Registers
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Application
      2. 9.2.2 Design Requirements
      3. 9.2.3 Detailed Design Procedure
      4. 9.2.4 Program Procedure
      5. 9.2.5 Application Performance Plots
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 接收文档更新通知
    2. 12.2 支持资源
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 术语表
  13. 13Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

8.6.5 FAULT Registers

Table 8-33 lists the FAULT registers, including Fault_state registers, LOD registers and LSD registers. All register offset addresses not listed in Table 8-33 must be considered as reserved locations and the register contents must not be modified.

Table 8-33 FAULT Registers
Address Acronym Register Name Section
64h Fault_state Global LOD/LSD indication register Go
65h Dot_lod0 LED dot LOD indication register 0 Go
66h Dot_lod1 LED dot LOD indication register 1 Go
67h Dot_lod2 LED dot LOD indication register 2 Go
86h Dot_lsd0 LED dot LSD indication register 0 Go
87h Dot_lsd1 LED dot LSD indication register 1 Go
88h Dot_lsd2 LED dot LSD indication register 2 Go

8.6.5.1 Fault_state Register (Address = 64h) [Default = 0h]

Fault_state is shown in Figure 8-37 and described in Table 8-34.

Return to the Summary Table.

Figure 8-37 Fault_state Register
7 6 5 4 3 2 1 0
RESERVED Global_LOD Global_LSD
R-0h R-0h R-0h
Table 8-34 Fault_state Register Field Descriptions
Bit Field Type Default Description
7-2 RESERVED R 0h Reserved
1 Global_LOD R 0h LOD indication bit if there is open fault detected at any LED dot
0h = Not open
1h = Open
0 Global_LSD R 0h LSD indication bit if there is short fault detected at any LED dot
0h = Not short
1h = Short

8.6.5.2 Dot_lod0 Register (Address = 65h) [Default = 0h]

Dot_lod0 is shown in Figure 8-38 and described in Table 8-35.

Return to the Summary Table.

Figure 8-38 Dot_lod0 Register
7 6 5 4 3 2 1 0
CS7_LOD_state CS6_LOD_state CS5_LOD_state CS4_LOD_state CS3_LOD_state CS2_LOD_state CS1_LOD_state CS0_LOD_state
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h
Table 8-35 Dot_lod0 Register Field Descriptions
Bit Field Type Default Description
7 CS7_LOD_state R 0h CS7 LOD state
0h = Not open
1h = Open
6 CS6_LOD_state R 0h CS6 LOD state
0h = Not open
1h = Open
5 CS5_LOD_state R 0h CS5 LOD state
0h = Not open
1h = Open
4 CS4_LOD_state R 0h CS4 LOD state
0h = Not open
1h = Open
3 CS3_LOD_state R 0h CS3 LOD state
0h = Not open
1h = Open
2 CS2_LOD_state R 0h CS2 LOD state
0h = Not open
1h = Open
1 CS1_LOD_state R 0h CS1 LOD state
0h = Not open
1h = Open
0 CS0_LOD_state R 0h CS0 LOD state
0h = Not open
1h = Open

8.6.5.3 Dot_lod1 Register (Address = 66h) [Default = 0h]

Dot_lod1 is shown in Figure 8-39 and described in Table 8-36.

Return to the Summary Table.

Figure 8-39 Dot_lod1 Register
7 6 5 4 3 2 1 0
CS15_LOD_state CS14_LOD_state CS13_LOD_state CS12_LOD_state CS11_LOD_state CS10_LOD_state CS9_LOD_state CS8_LOD_state
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h
Table 8-36 Dot_lod1 Register Field Descriptions
Bit Field Type Default Description
7 CS15_LOD_state R 0h CS15 LOD state
0h = Not open
1h = Open
6 CS14_LOD_state R 0h CS14 LOD state
0h = Not open
1h = Open
5 CS13_LOD_state R 0h CS13 LOD state
0h = Not open
1h = Open
4 CS12_LOD_state R 0h CS12 LOD state
0h = Not open
1h = Open
3 CS11_LOD_state R 0h CS11 LOD state
0h = Not open
1h = Open
2 CS10_LOD_state R 0h CS10 LOD state
0h = Not open
1h = Open
1 CS9_LOD_state R 0h CS9 LOD state
0h = Not open
1h = Open
0 CS8_LOD_state R 0h CS8 LOD state
0h = Not open
1h = Open

8.6.5.4 Dot_lod2 Register (Address = 67h) [Default = 0h]

Dot_lod2 is shown in Figure 8-40 and described in Table 8-37.

Return to the Summary Table.

Figure 8-40 Dot_lod2 Register
7 6 5 4 3 2 1 0
RESERVED CS17_LOD_state CS16_LOD_state
R-0h R-0h R-0h
Table 8-37 Dot_lod2 Register Field Descriptions
Bit Field Type Default Description
7-2 RESERVED R 0h Reserved
1 CS17_LOD_state R 0h CS17 LOD state
0h = Not open
1h = Open
0 CS16_LOD_state R 0h CS16 LOD state
0h = Not open
1h = Open

8.6.5.5 Dot_lsd0 Register (Address = 86h) [Default = 0h]

Dot_lsd0 is shown in Figure 8-41 and described in Table 8-38.

Return to the Summary Table.

Figure 8-41 Dot_lsd0 Register
7 6 5 4 3 2 1 0
CS7_LSD_state CS6_LSD_state CS5_LSD_state CS4_LSD_state CS3_LSD_state CS2_LSD_state CS1_LSD_state CS0_LSD_state
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h
Table 8-38 Dot_lsd0 Register Field Descriptions
Bit Field Type Default Description
7 CS7_LSD_state R 0h CS7 LSD state
0h = Not short
1h = Short
6 CS6_LSD_state R 0h CS6 LSD state
0h = Not short
1h = Short
5 CS5_LSD_state R 0h CS5 LSD state
0h = Not short
1h = Short
4 CS4_LSD_state R 0h CS4 LSD state
0h = Not short
1h = Short
3 CS3_LSD_state R 0h CS3 LSD state
0h = Not short
1h = Short
2 CS2_LSD_state R 0h CS2 LSD state
0h = Not short
1h = Short
1 CS1_LSD_state R 0h CS1 LSD state
0h = Not short
1h = Short
0 CS0_LSD_state R 0h CS0 LSD state
0h = Not short
1h = Short

8.6.5.6 Dot_lsd1 Register (Address = 87h) [Default = 0h]

Dot_lsd1 is shown in Figure 8-42 and described in Table 8-39.

Return to the Summary Table.

Figure 8-42 Dot_lsd1 Register
7 6 5 4 3 2 1 0
CS15_LSD_state CS14_LSD_state CS13_LSD_state CS12_LSD_state CS11_LSD_state CS10_LSD_state CS9_LSD_state CS8_LSD_state
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h
Table 8-39 Dot_lsd1 Register Field Descriptions
Bit Field Type Default Description
7 CS15_LSD_state R 0h CS15 LSD state
0h = Not short
1h = Short
6 CS14_LSD_state R 0h CS14 LSD state
0h = Not short
1h = Short
5 CS13_LSD_state R 0h CS13 LSD state
0h = Not short
1h = Short
4 CS12_LSD_state R 0h CS12 LSD state
0h = Not short
1h = Short
3 CS11_LSD_state R 0h CS11 LSD state
0h = Not short
1h = Short
2 CS10_LSD_state R 0h CS10 LSD state
0h = Not short
1h = Short
1 CS9_LSD_state R 0h CS9 LSD state
0h = Not short
1h = Short
0 CS8_LSD_state R 0h CS8 LSD state
0h = Not short
1h = Short

8.6.5.7 Dot_lsd2 Register (Address = 88h) [Default = 0h]

Dot_lsd2 is shown in Figure 8-43 and described in Table 8-40.

Return to the Summary Table.

Figure 8-43 Dot_lsd2 Register
7 6 5 4 3 2 1 0
RESERVED CS17_LSD_state CS16_LSD_state
R-0h R-0h R-0h
Table 8-40 Dot_lsd2 Register Field Descriptions
Bit Field Type Default Description
7-2 RESERVED R 0h Reserved
1 CS17_LSD_state R 0h CS17 LSD state
0h = Not short
1h = Short
0 CS16_LSD_state R 0h CS16 LSD state
0h = Not short
1h = Short