ZHCSOR5 January   2022 LP5861

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Analog Dimming (Current Gain Control)
      2. 8.3.2 PWM Dimming
      3. 8.3.3 ON and OFF Control
      4. 8.3.4 Data Refresh Mode
      5. 8.3.5 Full Addressable SRAM
      6. 8.3.6 Protections and Diagnostics
    4. 8.4 Device Functional Modes
    5. 8.5 Programming
    6. 8.6 Register Maps
      1. 8.6.1 CONFIG Registers
      2. 8.6.2 GROUP Registers
      3. 8.6.3 DOTGROUP Registers
      4. 8.6.4 DOTONOFF Registers
      5. 8.6.5 FAULT Registers
      6. 8.6.6 RESET Registers
      7. 8.6.7 DC Registers
      8. 8.6.8 PWM Registers
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Application
      2. 9.2.2 Design Requirements
      3. 9.2.3 Detailed Design Procedure
      4. 9.2.4 Program Procedure
      5. 9.2.5 Application Performance Plots
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 接收文档更新通知
    2. 12.2 支持资源
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 术语表
  13. 13Mechanical, Packaging, and Orderable Information

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8.6.1 CONFIG Registers

Table 8-9 lists the CONFIG registers. All register offset addresses not listed in Table 8-9 must be considered as reserved locations and the register contents must not be modified.

Table 8-9 CONFIG Registers
Address Acronym Register Name Section
0h Chip_en Chip enable Go
1h Dev_initial Device initialization Go
2h Dev_config1 Device configuration register 1 Go
3h Dev_config2 Device configuration register 2 Go
4h Dev_config3 Device configuration register 3 Go

8.6.1.1 Chip_en Register (Address = 0h) [Default = 0h]

Chip_en is shown in Figure 8-17 and described in Table 8-10.

Return to the Summary table.

Figure 8-17 Chip_en Register
7 6 5 4 3 2 1 0
RESERVED Chip_EN
R-0h R/W-0h
Table 8-10 Chip_en Register Field Descriptions
Bit Field Type Default Description
7-1 RESERVED R 0h Reserved
0 Chip_EN R/W 0h Chip enable
0h = Disabled
1h = Enabled

8.6.1.2 Dev_initial Register (Address = 1h) [Default = 5Eh]

Dev_initial is shown in Figure 8-18 and described in Table 8-11.

Return to the Summary table.

Figure 8-18 Dev_initial Register
7 6 5 4 3 2 1 0
RESERVED Data_Ref_Mode PWM_Fre
R-Bh R/W-3h R/W-0h
Table 8-11 Dev_initial Register Field Descriptions
Bit Field Type Default Description
7-3 RESERVED R Bh Reserved
2-1 Data_Ref_Mode R/W 3h Data refresh mode slection
0h = Mode 1
1h = Mode 2
2h = Mode 3
3h = Mode 3
0 PWM_Fre R/W 0h Output PWM frequency setting
0h = 125kHz
1h = 62.5kHz

8.6.1.3 Dev_config1 Register (Address = 2h) [Default = 0h]

Dev_config1 is shown in Figure 8-19 and described in Table 8-12.

Return to the Summary table.

Figure 8-19 Dev_config1 Register
7 6 5 4 3 2 1 0
RESERVED PWM_Scale_Mode PWM_Phase_Shift RESERVED
R-0h R/W-0h R/W-0h R-0h
Table 8-12 Dev_config1 Register Field Descriptions
Bit Field Type Default Description
7-3 RESERVED R 0h Reserved
2 PWM_Scale_Mode R/W 0h Dimming scale setting of final PWM generator
0h = Linear scale dimming curve
1h = Exponential scale dimming curve
1 PWM_Phase_Shift R/W 0h PWM phase shift selection
0h = Phase shift off
1h = Phase shift on
0 RESERVED R 0h Reserved

8.6.1.4 Dev_config2 Register (Address = 3h) [Default = 0h]

Dev_config2 is shown in Figure 8-20 and described in Table 8-13.

Return to the Summary table.

Figure 8-20 Dev_config2 Register
7 6 5 4 3 2 1 0
Comp_Group3 Comp_Group2 Comp_Group1 RESERVED
R/W-0h R/W-0h R/W-0h R-0h
Table 8-13 Dev_config2 Register Field Descriptions
Bit Field Type Default Description
7-6 Comp_Group3 R/W 0h Low brightness compensation clock shift number setting for group1
0h = off
1h = 1 clock
2h = 2 clock
3h = 3 clock
5-4 Comp_Group2 R/W 0h Low brightness compensation clock shift number setting for group2
0h = off
1h = 1 clock
2h = 2 clock
3h = 3 clock
3-2 Comp_Group1 R/W 0h Low brightness compensation clock shift number setting for group3
0h = off
1h = 1 clock
2h = 2 clock
3h = 3 clock
1-0 RESERVED R 0h Reserved

8.6.1.5 Dev_config3 Register (Address = 4h) [Default = 57h]

Dev_config3 is shown in Figure 8-21 and described in Table 8-14.

Return to the Summary table.

Figure 8-21 Dev_config3 Register
7 6 5 4 3 2 1 0
RESERVED Maximum_Current RESERVED
R-5h R/W-3h R-1h
Table 8-14 Dev_config3 Register Field Descriptions
Bit Field Type Default Description
7-4 RESERVED R 5h Reserved
3-1 Maximum_Current R/W 3h Maximum current cetting (MC)
0h = 3mA
1h = 5mA
2h = 10mA
3h = 15mA (Default)
4h = 20mA
5h = 30mA
6h = 40mA
7h = 50mA
0 RESERVED R 1h Reserved