SNVS087AE October   2000  – May 2015 LP3985


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Performance Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 No-Load Stability
      2. 7.3.2 On/Off Input Operation
      3. 7.3.3 Fast On-Time
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operation with VOUT(TARGET) + 0.3 V ≤ VIN ≤ 6 V
      2. 7.4.2 Operation Using the EN Pin
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. External Capacitors
        2. Input Capacitor
        3. Output Capacitor
        4. Capacitor Characteristics
        5. Noise Bypass Capacitor
        6. Thermal Considerations
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
    3. 10.3 DSBGA Mounting
    4. 10.4 DSBGA Light Sensitivity
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information


机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)

10 Layout

10.1 Layout Guidelines

For best overall performance, place all circuit components on the same side of the circuit board and as near as practical to the respective LDO pin connections. Place ground return connections to the input and output capacitor, and to the LDO ground pin as close to each other as possible, connected by a wide, component-side, copper surface. The use of vias and long traces to create LDO circuit connections is strongly discouraged and negatively affects system performance. This grounding and layout scheme minimizes inductive parasitics, and thereby reduces load-current transients, minimizes noise, and increases circuit stability. A ground reference plane is also recommended and is either embedded in the PCB itself or located on the bottom side of the PCB opposite the components. This reference plane serves to assure accuracy of the output voltage, shield noise, and behaves similar to a thermal plane to spread (or sink) heat from the LDO device. In most applications, this ground plane is necessary to meet thermal requirements.

10.2 Layout Examples

LP3985 layout_SOT23snvs087.gifFigure 41. LP3985 SOT-23 Package Typical Layout
LP3985 DSBGAlayout_snvs087.gifFigure 42. LP3985 DSBGA Package Typical Layout

10.3 DSBGA Mounting

The DSBGA package requires specific mounting techniques which are detailed in Texas Instruments Application Note 1112 DSBGA Wafer Level Chip Scale Package (SNVA009). Referring to the section Surface Mount Technology (SMT) Assembly Considerations, it should be noted that the pad style which must be used with the 5-bump package is NSMD (non-solder mask defined) type.

For best results during assembly, alignment ordinals on the PC board may be used to facilitate placement of the DSBGA device.

10.4 DSBGA Light Sensitivity

Exposing the DSBGA device to direct sunlight will cause mis-operation of the device. Light sources such as halogen lamps can effect electrical performance if brought near to the device.

The wavelengths which have most detrimental effect are reds and infra-reds, which means that the fluorescent lighting used inside most buildings has very little effect on performance. A DSBGA test board was brought to within 1 cm of a fluorescent desk lamp and the effect on the regulated output voltage was negligible, showing a deviation of less than 0.1% from nominal.