SNVS256D Novmeber   2003  – November 2016 LP3943

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Interface (SCL and SDA Pins) Timing Requirements
    7. 6.7 Typical Characteristic
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
      1. 7.5.1 I2C Data Validity
      2. 7.5.2 I2C START and STOP Conditions
      3. 7.5.3 Transferring Data
      4. 7.5.4 Auto Increment
    6. 7.6 Register Maps
      1. 7.6.1 Binary Format for Input Registers (Read-only)—Address 0x00 and 0x01
      2. 7.6.2 Binary Format for Frequency Prescaler and PWM Registers — Address 0x02 to 0x05
      3. 7.6.3 Binary Format for Selector Registers — Address 0x06 to 0x09
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Reducing IQ When LEDs are OFF
      3. 8.2.3 Application Curve
    3. 8.3 System Examples
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)(2)(3)
MIN MAX UNIT
VDD –0.5 6 V
A0, A1, A2, SCL, SDA, RST
(Collectively called digital pins)		 6 V
Voltage on LED pins VSS − 0.5 6 V
Junction temperature 150 °C
Power dissipation(4) 400 mW
Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to the potential at the GND pin.
(3) If Military/Aerospace specified devices are required, contact the Texas Instruments Sales Office/ Distributors for availability and specifications.
(4) The part cannot dissipate more than 400 mW.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1000
Machine model ±200
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)(1)(2)
MIN NOM MAX UNIT
VDD 2.3 5.5 V
Junction temperature –40 125 °C
Operating ambient temperature –40 85 °C
(1) Absolute Maximum Ratings are limits beyond which damage to the device might occur. Recommended Operating Conditions are conditions under which operation of the device is ensured. Recommended Operating Conditions do not imply ensured performance limits. For verified performance limits and associated test conditions, see Electrical Characteristics.
(2) All voltages are with respect to the potential at the GND pin.

6.4 Thermal Information

THERMAL METRIC(1) LP3943 UNIT
RTW (WQFN)
24 PINS
RθJA Junction-to-ambient thermal resistance 45.0 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 41.5 °C/W
RθJB Junction-to-board thermal resistance 22.4 °C/W
ψJT Junction-to-top characterization parameter 0.5 °C/W
ψJB Junction-to-board characterization parameter 22.5 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 3.7 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Electrical Characteristics

Unless otherwise noted, VDD = 5.5 V. Typical values and limits apply for TJ = 25°C. Minimum and maximum limits apply over the entire junction temperature range for operation, TJ = −40°C to +125°C.(1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER SUPPLY
VDD Supply voltage 2.3 5 5.5 V
IQ Supply current No load 350 550 µA
Standby 2 5
ΔIQ Additional standby current VDD = 5.5 V, every LED pin at 4.3 V 2 mA
VPOR Power-On Reset voltage 1.8 1.96 V
tw Reset pulse width 10 ns
LED
VIL Low level input voltage −0.5 0.8 V
VIH High level input voltage 2 5.5 V
IOL Low level output current(2) VOL = 0.4 V, VDD = 2.3 V 9 mA
VOL = 0.4 V, VDD = 3 V 12
VOL = 0.4 V, VDD = 5 V 15
VOL = 0.7 V, VDD = 2.3 V 15
VOL = 0.7 V, VDD = 3 V 20
VOL = 0.7 V, VDD = 5 V 25
ILEAK Input leakage current VDD = 3.6 V, VIN = 0 V or VDD −1 1 µA
CI/O Input/output capacitance See(3) 2.6 5 pF
ALL DIGITAL PINS (EXCEPT SCL AND SDA PINS)
VIL LOW level input voltage −0.5 0.8 V
VIH HIGH level input voltage 2 5.5 V
ILEAK Input leakage current −1 1 µA
CIN Input capacitance VIN = 0 V(3) 2.3 5 pF
I2C INTERFACE (SCL AND SDA PINS)
VIL LOW level input voltage –0.5 0.3VDD V
VIH HIGH level input voltage 0.7VDD 5.5 V
VOL LOW level output voltage 0 0.2VDD V
IOL LOW level output current VOL = 0.4 V 3 6.5 mA
ƒCLK Clock frequency 400 kHz
(1) Limits are ensured. All electrical characteristics having room-temperature limits are tested during production with TJ = 25°C. All hot and cold limits are ensured by correlating the electrical characteristics to process and temperature variations and applying statistical process control.
(2) Each LED pin must not exceed 25 mA and each octal (LED0–LED7; LED8–LED15) must not exceed 100 mA. The package must not exceed a total of 200 mA.
(3) Verified by design.

6.6 I2C Interface (SCL and SDA Pins) Timing Requirements

See(1)
MIN NOM MAX UNIT
tHOLD Hold time repeated START condition 0.6 µs
tCLK-LP CLK low period 1.3 µs
tCLK-HP CLK high period 0.6 µs
tSU Setup time repeated START condition 0.6 µs
tDATA-HOLD Data hold time 300 ns
tDATA-SU Data setup time 100 ns
tSU Setup time for STOP condition 0.6 µs
tTRANS Maximum pulse width of spikes that must be suppressed by the input filter of both DATA and CLK signals 50 ns
(1) All values verified by design.

6.7 Typical Characteristic

LP3943 20079617.gif
TA = −40°C to +85°C VDD = 2.3 V to 3 V
Figure 1. Frequency vs. Temperature