10.1 Layout Guidelines

PCB layout is an important part of DC-DC converter design. Poor board layout can disrupt the performance of a DC-DC converter and surrounding circuitry by contributing to EMI, ground bounce and resistive voltage drop in the traces. These can send erroneous signals to the DC-DC converter resulting in poor regulation or instability. Good layout can be implemented by following a few simple design rules.

1. Minimize area of switched current loops.

From an EMI reduction standpoint, it is imperative to minimize the high di/dt paths during PCB layout. The high current loops that do not overlap have high di/dt content that will cause observable high frequency noise on the output pin if the input capacitor (Cin1) is placed at a distance away from the LMZ14203. Therefore place C_IN1 as close as possible to the LMZ14203 VIN and GND exposed pad. This will minimize the high di/dt area and reduce radiated EMI. Additionally, grounding for both the input and output capacitor should consist of a localized top side plane that connects to the GND exposed pad (EP).

2. Have a single point ground.

The ground connections for the feedback, soft-start, and enable components should be routed to the GND pin of the device. This prevents any switched or load currents from flowing in the analog ground traces. If not properly handled, poor grounding can result in degraded load regulation or erratic output voltage ripple behavior. Provide the single point ground connection from pin 4 to EP.

3. Minimize trace length to the FB pin.

Both feedback resistors, R_FBT and R_FBB, and the feed forward capacitor C_FF, should be close to the FB pin. Since the FB node is high impedance, maintain the copper area as small as possible. The trace are from R_FBT, R_FBB, and C_FF should be routed away from the body of the LMZ14203 to minimize noise.

4. Make input and output bus connections as wide as possible.

This reduces any voltage drops on the input or output of the converter and maximizes efficiency. To optimize voltage accuracy at the load, ensure that a separate feedback voltage sense trace is made to the load. Doing so will correct for voltage drops and provide optimum output accuracy.

5. Provide adequate device heat-sinking.

Use an array of heat-sinking vias to connect the exposed pad to the ground plane on the bottom PCB layer. If the PCB has a plurality of copper layers, these thermal vias can also be employed to make connection to inner layer heat-spreading ground planes. For best results use a 6 × 6 via array with minimum via diameter of 8 mils thermal vias spaced 59 mils (1.5 mm). Ensure enough copper area is used for heat-sinking to keep the junction temperature below 125°C.

10.1.1 Power Module SMT Guidelines

The recommendations below are for a standard module surface mount assembly

• Land Pattern – Follow the PCB land pattern with either soldermask defined or non-soldermask defined pads
• Stencil Aperture
  • For the exposed die attach pad (DAP), adjust the stencil for approximately 80% coverage of the PCB land pattern
  • For all other I/O pads use a 1:1 ratio between the aperture and the land pattern recommendation
• Solder Paste – Use a standard SAC Alloy such as SAC 305, type 3 or higher
• Stencil Thickness – 0.125 mm to 0.15 mm
• Reflow - Refer to solder paste supplier recommendation and optimized per board size and density
• Refer to AN Design Summary LMZ1xxx and LMZ2xxx Power Modules Family (SNAA214) for Reflow information.
• Maximum number of reflows allowed is one

Figure 48. Sample Reflow Profile

Table 1. Sample Reflow Profile Table

PROBE	MAX TEMP (°C)	REACHED MAX TEMP	TIME ABOVE 235°C	REACHED 235°C	TIME ABOVE 245°C	REACHED 245°C	TIME ABOVE 260°C	REACHED 260°C
1	242.5	6.58	0.49	6.39	0	–	0	–
2	242.5	7.1	0.55	6.31	0	7.1	0	–
3	241	7.09	0.42	6.44	0	–	0	–

10.2 Layout Example

Figure 49. Minimize Area of Current Loops in Buck Module

Figure 50. PCB Layout Guide

10.3 Power Dissipation and Board Thermal Requirements

For a design case of V_IN = 24 V, V_OUT = 12 V, I_OUT = 3 A, T_A (MAX) = 65°C , and T_JUNCTION = 125°C, the device must see a maximum junction-to-ambient thermal resistance of:

This R_θJA-MAX will ensure that the junction temperature of the regulator does not exceed T_J-MAX in the particular application ambient temperature.

To calculate the required R_θJA-MAX we need to get an estimate for the power losses in the IC. The following graph is taken form the Typical Characteristics section (Figure 16) and shows the power dissipation of the LMZ14203H for V_OUT = 12 V at 85°C T_A.

Figure 51. Power Dissipation V_OUT = 12V T_A = 85°C

Using the 85°C T_A power dissipation data as a conservative starting point, the power dissipation P_D for V_IN = 24 V and V_OUT = 12V is estimated to be 3.5W. The necessary R_θJA-MAX can now be calculated.

To achieve this thermal resistance the PCB is required to dissipate the heat effectively. The area of the PCB will have a direct effect on the overall junction-to-ambient thermal resistance. In order to estimate the necessary copper area we can refer to Figure 52. This graph is taken from the Typical Characteristics section (Figure 31) and shows how the R_θJA varies with the PCB area.

Figure 52. Package Thermal Resistance R_θJA 4-Layer PCB With 1-oz Copper

For R_θJA-MAX< 17.1°C/W and only natural convection (that is., no air flow), the PCB area will have to be at least 52 cm². This corresponds to a square board with 7.25 cm x 7.25 cm (2.85 in x 2.85 in) copper area, 4 layers, and 1oz copper thickness. Higher copper thickness will further improve the overall thermal performance. As a reference, the evaluation board has 2-oz copper on the top and bottom layers, achieving R_θJA of 14.9°C/W for the same board area. Note thermal vias should be placed under the IC package to easily transfer heat from the top layer of the PCB to the inner layers and the bottom layer.

For more guidelines and insight on PCB copper area, thermal vias placement, and general thermal design practices see the application note, AN-2020 Thermal Design By Insight, Not Hindsight (SNVA419).