ZHCSH13 数据表 | 德州仪器 TI.com.cn

ZHCSH13B October 2017 – January 2019 LMX2572

PRODUCTION DATA.

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RHA|40
- MPQF135D

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RHA|40
- QFND114P

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6.5 Electrical Characteristics

3.0 V ≤ V_CC ≤ 3.5 V, –40°C ≤ T_A ≤ 85°C. Typical values are at V_CC = 3.3 V, 25°C (unless otherwise noted)

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
POWER SUPPLY
V_CC	Supply voltage			3	3.3	3.5	V
I_CC	Supply current	f_PD = 20 MHz; I_CPout = 1.25 mA	Direct VCO output⁽¹⁾		75		mA
		f_PD = 100 MHz; I_CPout = 2.5 mA	Direct VCO output⁽¹⁾		79
		f_PD = 20 MHz; I_CPout = 1.25 mA	Divided down output⁽²⁾		82
		f_PD = 100 MHz; I_CPout = 2.5 mA	Divided down output⁽²⁾		86
I_CCPD	Power down current				2.5
INPUT SIGNAL PATH
f_OSCin	OSCin input frequency	OSC_2X = 0 (Doubler bypassed)		5		250	MHz
f_OSCin	OSCin input frequency	OSC_2X = 1 (Doubler enabled)		5		125	MHz
V_OSCin	OSCin input voltage⁽³⁾	Single-ended input buffer		0.3		3.6	V
V_OSCin	OSCin input voltage⁽³⁾	Differential input buffer		0.15		1	V
f_MULTin	Multiplier input frequency	MULT ≥ 3		10		40	MHz
f_MULTout	Multiplier output frequency	MULT ≥ 3		60		150	MHz
PLL
f_PD	Phase detector frequency⁽⁴⁾	Integer channel		0.25		250	MHz
		1^st and 2^nd order modulator		5		200
		3^rd order modulator		5		160
		4^th order modulator		5		120
I_CPout	Charge pump current	CPG = 1			625		µA
		CPG = 2			1250
		CPG = 3			1875
		···			···
		CPG = 15			6875
PN_{PLL_1/f}	Normalized PLL 1/f noise⁽⁵⁾				–123.5		dBc/Hz
PN_{PLL_Flat}	Normalized PLL noise floor⁽⁵⁾	Integer channel⁽⁶⁾			–232
PN_{PLL_Flat}	Normalized PLL noise floor⁽⁵⁾	Fractional channel⁽⁷⁾			–232
VCO
f_VCO	VCO frequency			3200		6400	MHz
PN_VCO	Open loop VCO phase noise	f_VCO = 3.4 GHz	10 kHz		–88		dBc/Hz
			100 kHz		–111
			1 MHz		–131
			10 MHz		–150
		f_VCO = 3.9 GHz	10 kHz		–87.5
			100 kHz		–111
			1 MHz		–131.5
			10 MHz		–150
		f_VCO = 4.4 GHz	10 kHz		–86.5
			100 kHz		–111
			1 MHz		–131
			10 MHz		–150
		f_VCO = 4.9 GHz	10 kHz		–85
			100 kHz		–110
			1 MHz		–130.5
			10 MHz		–149.5
		f_VCO = 5.4 GHz	10 kHz		–84.5
			100 kHz		–109
			1 MHz		–129.5
			10 MHz		–149
		f_VCO = 5.9 GHz	10 kHz		–84
			100 kHz		–108.5
			1 MHz		–129
			10 MHz		–148
K_VCO	VCO gain	f_VCO = 3.4 GHz			39		MHz/V
		f_VCO = 3.9 GHz			44
		f_VCO = 4.4 GHz			55
		f_VCO = 4.9 GHz			60
		f_VCO = 5.4 GHz			69
		f_VCO = 5.9 GHz			62
t_VCOcal	VCO calibration-time⁽⁸⁾	f_OSCin = f_PD = 100 MHz; Switch between 3.2 GHz and 6.4 GHz	No assist		130		µs
			Partial assist		50
			Full assist		5
\|Δ_TCL\|	Allowable temperature drift⁽⁹⁾	VCO not being re-calibrated, –40°C ≤ T_A ≤ 85°C				125	°C
RF OUTPUT
f_OUT	RF output frequency			12.5		6400	MHz
P_OUT	Single-ended output power	f_OUT = 6.4GHz	OUTx_PWR = 50		4.5		dBm
H2_OUT	Second harmonic	f_VCO = f_OUT = 6.4 GHz			–20		dBc
H2_OUT	Second harmonic	f_VCO = 6.4 GHz, f_OUT = 3.2 GHz			–37
H3_OUT	Third harmonic	f_VCO = f_OUT = 6.4 GHz			–25
H3_OUT	Third harmonic	f_VCO = 6.4 GHz, f_OUT = 3.2 GHz			–13
\|t_skewCH\|	Channel to channel skew	f_OUT = 3.2 GHz			14		ps
PHASE SYNCHRONIZATION
f_OSCinSYNC	OSCin input frequency with SYNC	Category 3		5		100	MHz
f_OSCinSYNC	OSCin input frequency with SYNC	Categories 1 and 2		5		200	MHz
\|t_skewSYNC\|	OSCin to RFout skew	After phase synchronization; f_OSCinSYNC = f_OUT = 100 MHz			2		ns
DIGITAL INTERFACE
V_IH	High-level input voltage			1.4		V_CC	V
V_IL	Low-level input voltage					0.4	V
I_IH	High-level input current			–25		25	µA
I_IL	Low-level input current			–25		25	µA
V_OH	High-level output voltage	Load current = –5 mA	MUXout pin	V_CC – 0.5			V
V_OL	Low-level output voltage	Load current = 5 mA	MUXout pin			0.5	V

(1) f_OSCin = 100 MHz; f_VCO = f_OUT = 6.4 GHz; P_OUT = 0 dBm; OSC_2X = 0; MULT = 1; one RF output.

(2) f_OSCin = 100 MHz; f_VCO = 6.4 GHz; f_OUT = 3.2 GHz; P_OUT = 0 dBm; OSC_2X = 0; MULT = 1; one RF output.

(3) See OSCin Configuration for definition of OSCin input voltage.

(4) For lower VCO frequencies, the N-divider minimum value can limit the phase detector frequency.

(5) Measured with a clean OSCin signal with a high slew rate using a wide loop bandwidth. The noise metrics model the PLL noise for an infinite loop bandwidth as: PLL_Total = 10*log[10^{(PLL_Flat/10)}+10^{(PLL_Flicker/10)}]; PLL_Flat = PN1 Hz + 20*log(N) + 10*log(f_PD); PLL_Flicker = PN10 kHz - 10*log(Offset/10 kHz) + 20*log(f_OUT/1 GHz)

(6) f_OSCin = 200 MHz; f_PD = 100 MHz; f_VCO= f_OUT= 6 GHz

(7) f_OSCin = 200 MHz; f_PD = 100 MHz; f_VCO= f_OUT= 6.001 GHz; Fractional denominator = 1000.

(8) See VCO Calibration for details.

(9) Not tested in production. Ensured by characterization. Allowable temperature drift refers to programming the device at an initial temperature and allowing this temperature to drift WITHOUT reprogramming the device, and still have the device stay at lock. This change could be up or down in temperature and the specification does not apply to temperatures that go outside the recommended operating temperatures of the device.