ZHCSEI5A March   2013  – January 2016 LMX2485Q-Q1

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用范围
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings - Commercial
    3. 6.3 ESD Ratings - Automotive
    4. 6.4 Recommended Operating Conditions
    5. 6.5 Thermal Information
    6. 6.6 Electrical Characteristics
    7. 6.7 Timing Characteristics
    8. 6.8 Typical Characteristics
      1. 6.8.1 Sensitivity
      2. 6.8.2 FinRF Input Impedance
      3. 6.8.3 FinIF Input Impedance
      4. 6.8.4 OSCin Input Impedance
      5. 6.8.5 Currents
  7. 7 Parameter Measurement Information
    1. 7.1 Bench Test Set-Ups
      1. 7.1.1 Charge Pump Current Measurement Procedure
      2. 7.1.2 Charge Pump Current Specification Definitions
        1. 7.1.2.1 Charge Pump Output Current Variation vs Charge Pump Output Voltage
        2. 7.1.2.2 Charge Pump Sink Current vs Charge Pump Output Source Current Mismatch
        3. 7.1.2.3 Charge Pump Output Current Variation vs Temperature
      3. 7.1.3 Sensitivity Measurement Procedure
      4. 7.1.4 Input Impedance Measurement Procedure
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Tcxo, Oscillator Buffer, and R Counter
      2. 8.3.2 Phase Detector
      3. 8.3.3 Charge Pump
      4. 8.3.4 Loop Filter
      5. 8.3.5 N Counters and High Frequency Input Pins
        1. 8.3.5.1 High Frequency Input Pins, FinRF and FinIF
        2. 8.3.5.2 Complementary High Frequency Pin, FinRF*
      6. 8.3.6 Digital Lock Detect Operation
      7. 8.3.7 Cycle Slip Reduction and Fastlock
        1. 8.3.7.1 Cycle Slip Reduction (CSR)
        2. 8.3.7.2 Fastlock
        3. 8.3.7.3 Using Cycle Slip Reduction (CSR) to Avoid Cycle Slipping
        4. 8.3.7.4 Using Fastlock to Improve Lock Times
        5. 8.3.7.5 Capacitor Dielectric Considerations for Lock Time
      8. 8.3.8 Fractional Spur and Phase Noise Controls
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power Pins, Power Down, and Power Up Modes
    5. 8.5 Programming
      1. 8.5.1 Register Location Truth Table
      2. 8.5.2 Control Register Content Map
    6. 8.6 Register Maps
      1. 8.6.1 R0 Register
      2. 8.6.2 R1 Register
      3. 8.6.3 R2 Register
      4. 8.6.4 R3 Register
      5. 8.6.5 R4 Register
      6. 8.6.6 R5 Register
      7. 8.6.7 R6 Register
      8. 8.6.8 R7 Register
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 社区资源
    2. 12.2 商标
    3. 12.3 静电放电警告
    4. 12.4 Glossary
  13. 13机械、封装和可订购信息

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • RTW|24
散热焊盘机械数据 (封装 | 引脚)
订购信息

5 Pin Configuration and Functions

RTW Package
24-Pin WQFN
Top View
LMX2485Q-Q1 30193622.gif

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
CE 10 I Chip Enable control pin. Must be pulled high for normal operation.
CLK 8 I MICROWIRE Clock. High-impedance CMOS Clock input. Data for the various counters is clocked into the 24 bit shift register on the rising edge
CPoutIF 16 O IF PLL charge pump output
CPoutRF 1 O RF PLL charge pump output.
DATA 7 I MICROWIRE Data. High-impedance binary serial data input.
ENOSC 19 I Oscillator enable. When this is set to high, the OSCout pin is enabled regardless of the state of other pins or register bits.
FinIF 13 I IF PLL high-frequency input pin.
FinRF 4 I RF PLL high-frequency input pin.
FinRF* 5 I RF PLL complementary high-frequency input pin. Shunt to ground with a 100-pF capacitor.
FLoutRF 23 O RF PLL Fastlock Output. Also functions as Programmable TRI-STATE CMOS output.
Ftest/LD 12 O Test frequency output / Lock Detect.
GND 0 — Ground Substrate. This is on the bottom of the package and must be grounded.
GND 2 — RF PLL analog ground.
GND 15 — IF PLL digital ground.
LE 6 I MICROWIRE Load Enable. High impedance CMOS input. Data stored in the shift registers is loaded into the internal latches when LE goes HIGH
NC 21 I This pin must be left open.
OSCin 20 I Input for TCXO signal.
OSCout 18 O Buffered output of the OSCin signal.
VddRF1 3 — RF PLL analog power supply.
VddRF2 9 — Power supply for RF PLL digital circuitry.
VddRF3 22 — Power supply for RF PLL digital circuitry.
VddRF4 24 — RF PLL analog power supply.
VddIF1 14 — IF PLL analog power supply.
VddIF2 17 — IF PLL power supply.