ZHCSP51B december   2020  – may 2023 LMR43610 , LMR43620

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Revision History
  6. 5 Device Comparison Table
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 System Characteristics
    7. 7.7 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Enable, Start-Up, and Shutdown
      2. 8.3.2  External CLK SYNC (with MODE/SYNC)
        1. 8.3.2.1 Pulse-Dependent MODE/SYNC Pin Control
      3. 8.3.3  Adjustable Switching Frequency (with RT)
      4. 8.3.4  Power-Good Output Operation
      5. 8.3.5  Internal LDO, VCC, and VOUT/FB Input
      6. 8.3.6  Bootstrap Voltage and VBOOT-UVLO (BOOT Terminal)
      7. 8.3.7  Output Voltage Selection
      8. 8.3.8  Soft Start and Recovery from Dropout
        1. 8.3.8.1 Recovery from Dropout
      9. 8.3.9  Current Limit and Short Circuit
      10. 8.3.10 Thermal Shutdown
      11. 8.3.11 Input Supply Current
    4. 8.4 Device Functional Modes
      1. 8.4.1 Shutdown Mode
      2. 8.4.2 Standby Mode
      3. 8.4.3 Active Mode
        1. 8.4.3.1 CCM Mode
        2. 8.4.3.2 Auto Mode – Light-Load Operation
          1. 8.4.3.2.1 Diode Emulation
          2. 8.4.3.2.2 Frequency Reduction
        3. 8.4.3.3 FPWM Mode – Light-Load Operation
        4. 8.4.3.4 Minimum On-Time (High Input Voltage) Operation
        5. 8.4.3.5 Dropout
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Choosing the Switching Frequency
        2. 9.2.2.2 Setting the Output Voltage
          1. 9.2.2.2.1 FB for Adjustable Output
        3. 9.2.2.3 Inductor Selection
        4. 9.2.2.4 Output Capacitor Selection
        5. 9.2.2.5 Input Capacitor Selection
        6. 9.2.2.6 CBOOT
        7. 9.2.2.7 VCC
        8. 9.2.2.8 CFF Selection
          1. 9.2.2.8.1 External UVLO
        9. 9.2.2.9 Maximum Ambient Temperature
      3. 9.2.3 Application Curves
    3. 9.3 Best Design Practices
    4. 9.4 Power Supply Recommendations
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
        1. 9.5.1.1 Ground and Thermal Considerations
      2. 9.5.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 第三方产品免责声明
      2. 10.1.2 Device Nomenclature
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 支持资源
    4. 10.4 Trademarks
    5. 10.5 静电放电警告
    6. 10.6 术语表
  12. 11Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
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订购信息

7.6 System Characteristics

The following specifications apply only to the typical applications circuit, with nominal component values. Specifications in the typical (TYP) column apply to TJ = 25°C only. Specifications in the minimum (MIN) and maximum (MAX) columns apply to the case of typical components over the temperature range of TJ = –40°C to 150°C. These specifications are not ensured by production testing.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENT
IQVIN Input current to VIN VIN = 13.5 V, Fixed 3.3-V VOUT, IOUT = 0 A, Auto mode 1.5 µA
VIN = 13.5 V, Fixed 5-V VOUT, IOUT = 0 A, Auto mode 2 µA
POWER STAGE
VDROP1 Input to output voltage differential to maintain VOUT regulation ≥ 95%, with frequency foldback VOUT = 3.3-V, fixed 2.2 MHz, IOUT = 1 A 0.2 V
VOUT = 5-V, fixed 2.2 MHz, IOUT = 1 A 0.2 V
VDROP2 Input to output voltage differential to maintain VOUT regulation ≥ 95% and FSW ≥ 1.85 MHz VOUT = 3.3-V, fixed 2.2 MHz, IOUT = 1 A 0.7 V
Input to output voltage differential to maintain VOUT regulation ≥ 95% and FSW ≥ 1.85 MHz VOUT = 5-V, fixed 2.2 MHz trim, IOUT = 1 A 0.9 V
DMAX Maximum switch duty cycle While in frequency fold-back 98 %
Fsw = 1.85 MHz, VOUT = 5.0-V, IOUT = 1 A 87 %
RFBPARA(min) Minimum value of the parallel feedback resistors: RFBT//RFBB 5 kΩ
PROTECTION
TSD(trip) Thermal shutdown temperature Shutdown temperature 158 168 186 °C
TSD(hyst) Thermal shutdown temperature Recovery temperature 15 20 °C