SNOSAW6E January   2008  – December 2014 LMP7721

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics: 2.5 V
    6. 6.6 Electrical Characteristics: 5 V
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Ultra-Low Input Bias Current
      2. 7.3.2 Wide Bandwidth at Low-Supply Current
      3. 7.3.3 Low Input Referred Noise
      4. 7.3.4 Low-Supply Voltage
      5. 7.3.5 Rail-to-Rail Output and Ground Sensing
      6. 7.3.6 Unique Pinout
      7. 7.3.7 Input Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Compensating Input Capacitance
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Using a Guard
      2. 8.1.2 Use Triaxial Cable
      3. 8.1.3 Properly Clean the Assembly
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

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6 Specifications

6.1 Absolute Maximum Ratings(1)(4)

MIN MAX UNIT
VIN Differential –0.3 0.3 V
Supply Voltage (VS = V+ – V−) (3) –0.3 6.0 V
Voltage on Input/Output Pins V+ + 0.3 V− − 0.3 V
Junction Temperature (2) 150 °C
Soldering Information
 Infrared or Convection (20 sec) 235 °C
 Wave Soldering Lead Temp. (10 sec) 260 °C
Storage temperature, Tstg −65 150 °C
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Recommended Operating Conditions indicate conditions for which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test conditions, see the Electrical Characteristics Tables.
(2) The maximum power dissipation is a function of TJ(MAX), θJA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(MAX) - TA)/θJA. All numbers apply for packages soldered directly onto a PC Board.
(3) The voltage on any pin should not exceed 6V relative to any other pins.
(4) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and specifications.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±200
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

MIN MAX UNIT
Temperature Range(2) –40 125 °C
Supply Voltage (VS = V+ – V−):
  0°C ≤ TA ≤ 125°C 1.8 5.5 V
 −40°C ≤ TA ≤ 125°C 2.0 5.5 V

6.4 Thermal Information

THERMAL METRIC(1) LMP7721 UNIT
D
8 PINS
RθJA Junction-to-ambient thermal resistance 190 °C/W
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics: 2.5 V

Unless otherwise specified, all limits are specified for TA = 25°C, V+ = 2.5 V, V− = 0 V, VCM = (V+ + V−)/2.
PARAMETER TEST CONDITIONS MIN(2) TYP(1) MAX(2) UNIT
VOS Input Offset Voltage –180 ±50 180 μV
–40°C ≤ TJ ≤ 125°C –480 480
TC VOS Input Offset Voltage Drift
(3)		 –1.5 –4 μV/°C
IBIAS Input Bias Current VCM = 1 V(4)(5) 25°C –20 ±3 20 fA
−40°C to 85°C –900 900
−40°C to 125°C –5 5 pA
IOS Input Offset Current VCM = 1 V(5) ±6 ±40 fA
CMRR Common-Mode Rejection Ratio 0 V ≤ VCM ≤ 1.4 V 83 100 dB
0 V ≤ VCM ≤ 1.4 V, –40°C ≤ TJ ≤ 125°C 80
PSRR Power Supply Rejection Ratio 1.8 V ≤ V+ ≤ 5.5 V, V− = 0 V, VCM = 0 84 92 dB
1.8 V ≤ V+ ≤ 5.5 V, V− = 0 V, VCM = 0, –40°C ≤ TJ ≤ 125°C 80
CMVR Input Common-Mode Voltage Range CMRR ≥ 80 dB −0.3 1.5 V
CMRR ≥ 78 dB, –40°C ≤ TJ ≤ 125°C –0.3 1.5
AVOL Large Signal Voltage Gain VO = 0.15 V to 2.2 V, RL = 2 kΩ to V+/2 88 107 dB
VO = 0.15 V to 2.2 V, RL = 2 kΩ to V+/2, –40°C ≤ TJ ≤ 125°C 82
VO = 0.15 V to 2.2 V, RL = 10 kΩ to V+/2 92 120
VO = 0.15 V to 2.2 V, RL = 10 kΩ to V+/2, –40°C ≤ TJ ≤ 125°C 88
VO Output Swing High RL = 2 kΩ to V+/2 70 25 mV
from V+
RL = 2 kΩ to V+/2, –40°C ≤ TJ ≤ 125°C 77
RL = 10 kΩ to V+/2 60 20
RL = 10 kΩ to V+/2, –40°C ≤ TJ ≤ 125°C 66
Output Swing Low RL = 2 kΩ to V+/2 30 70 mV
RL = 2 kΩ to V+/2, –40°C ≤ TJ ≤ 125°C 73
RL = 10 kΩ to V+/2 15 60
RL = 10 kΩ to V+/2, –40°C ≤ TJ ≤ 125°C 62
IO Output Short Circuit Current Sourcing to V−, VIN = 200 mV (6) 36 46 mA
Sourcing to V−, VIN = 200 mV (6), –40°C ≤ TJ ≤ 125°C 30
Sinking to V+, VIN = −200 mV (6) 7.5 15
Sinking to V+, VIN = −200 mV (6), –40°C ≤ TJ ≤ 125°C 5.0
IS Supply Current 1.1 1.5 mA
–40°C ≤ TJ ≤ 125°C 1.75
SR Slew Rate AV = +1, Rising (10% to 90%) 9.3 V/μs
AV = +1, Falling (90% to 10%) 10.8
GBW Gain Bandwidth Product 15 MHz
en Input-Referred Voltage Noise f = 400 Hz 8 nV/20204099.png
f = 1 kHz 7
In Input-Referred Current Noise f = 1 kHz 0.01 pA/20204099.png
THD+N Total Harmonic Distortion + Noise f = 1 kHz, AV = 2, RL = 100 kΩ
VO = 0.9 VPP		 0.003%
f = 1 kHz, AV = 2, RL = 600 Ω
VO = 0.9 VPP		 0.003%

6.6 Electrical Characteristics: 5 V

Unless otherwise specified, all limits are specified for TA = 25°C, V+ = 5 V, V− = 0 V, VCM = (V+ + V−)/2.
PARAMETER TEST CONDITIONS MIN(2) TYP(1) MAX(2) UNIT
VOS Input Offset Voltage –150 ±26 150 μV
–40°C ≤ TJ ≤ 125°C 450 450
TC VOS Input Offset Average Drift
(3)		 –1.5 –4 μV/°C
IBIAS Input Bias Current VCM = 1 V(4)(5) 25°C –20 ±3 20 fA
−40°C to 85°C –900 900
−40°C to 125°C –5 5 pA
IOS Input Offset Current (5) ±6 ±40 fA
CMRR Common-Mode Rejection Ratio 0 V ≤ VCM ≤ 3.7 V 84 100 dB
0 V ≤ VCM ≤ 3.7 V, –40°C ≤ TJ ≤ 125°C 82
PSRR Power Supply Rejection Ratio 1.8 V ≤ V+ ≤ 5.5 V, V− = 0 V, VCM = 0 84 96 dB
1.8 V ≤ V+ ≤ 5.5 V, V− = 0 V, VCM = 0, –40°C ≤ TJ ≤ 125°C 80
CMVR Input Common-Mode Voltage Range CMRR ≥ 80 dB −0.3 4 V
CMRR ≥ 78 dB, –40°C ≤ TJ ≤ 125°C –0.3 4
AVOL Large Signal Voltage Gain VO = 0.3 V to 4.7 V, RL = 2 kΩ to V+/2 88 111 dB
VO = 0.3 V to 4.7 V, RL = 2 kΩ to V+/2, –40°C ≤ TJ ≤ 125°C 82
VO = 0.3 V to 4.7 V, RL = 10 kΩ to V+/2 92 120
VO = 0.3 V to 4.7 V, RL = 10 kΩ to V+/2, –40°C ≤ TJ ≤ 125°C 88
VO Output Swing High RL = 2 kΩ to V+/2 70 30 mV
from V+
RL = 2 kΩ to V+/2, –40°C ≤ TJ ≤ 125°C 77
RL = 10 kΩ to V+/2 60 20
RL = 10 kΩ to V+/2, –40°C ≤ TJ ≤ 125°C 66
Output Swing Low RL = 2 kΩ to V+/2 31 70 mV
RL = 2 kΩ to V+/2, –40°C ≤ TJ ≤ 125°C 73
RL = 10 kΩ to V+/2 20 60
RL = 10 kΩ to V+/2, –40°C ≤ TJ ≤ 125°C 62
IO Output Short Circuit Current Sourcing to V−, VIN = 200 mV (6) 46 60 mA
Sourcing to V−, VIN = 200 mV (6), –40°C ≤ TJ ≤ 125°C 38
Sinking to V+, VIN = −200 mV (6) 10.5 22
Sinking to V+, VIN = −200 mV (6), –40°C ≤ TJ ≤ 125°C 6.5
IS Supply Current 1.3 1.7 mA
–40°C ≤ TJ ≤ 125°C 1.95
SR Slew Rate AV = +1, Rising (10% to 90%) 10.43 V/μs
AV = +1, Falling (90% to 10%) 12.76
GBW Gain Bandwidth Product 17 MHz
en Input-Referred Voltage Noise f = 400 Hz 7.5 nV/20204099.png
f = 1 kHz 6.5
In Input-Referred Current Noise f = 1 kHz 0.01 pA/20204099.png
THD+N Total Harmonic Distortion + Noise f = 1 kHz, AV = 2, RL = 100 kΩ
VO = 4 VPP		 0.0007%
f = 1 kHz, AV = 2, RL = 600Ω
VO = 4 VPP		 0.0007%
(1) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and will also depend on the application and configuration. The typical values are not tested and are not specified on shipped production material.
(2) Limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlations using the Statistical Quality Control (SQC) method.
(3) Offset voltage average drift is determined by dividing the change in VOS at the temperature extremes by the total temperature change.
(4) Positive current corresponds to current flowing into the device.
(5) This parameter is specified by design and/or characterization and is not tested in production.
(6) The short circuit test is a momentary open loop test.

6.7 Typical Characteristics

Unless otherwise specified: TA = 25°C, VCM = (V+ + V−)/2.
20204094.gifFigure 1. Input Bias Current vs. VCM
20204095.gifFigure 3. Input Bias Current vs. VCM
20204085.gifFigure 5. Input Bias Current vs. VCM
20204040.gifFigure 7. Offset Voltage Distribution
20204046.gifFigure 9. TCVOS Distribution
20204022.gifFigure 11. Offset Voltage vs. VCM
20204019.gifFigure 13. Offset Voltage vs. Supply Voltage
20204038.gifFigure 15. Supply Current vs. Supply Voltage
20204014.gifFigure 17. Open-Loop Frequency Response Gain and Phase
20204016.gifFigure 19. Phase Margin vs. Capacitive Load
20204041.gifFigure 21. PSRR vs. Frequency
20204010.gifFigure 23. Time Domain Voltage Noise
20204004.gifFigure 25. Small Signal Step Response
20204005.gifFigure 27. Large Signal Step Response
20204007.gifFigure 29. THD+N vs. Output Voltage
20204009.gifFigure 31. THD+N vs. Frequency
20204033.gifFigure 33. Sinking Current vs. Supply Voltage
20204035.gifFigure 35. Sourcing Current vs. Output Voltage
20204032.gifFigure 37. Sinking Current vs. Output Voltage
20204029.gifFigure 39. Output Swing Low vs. Supply Voltage
20204028.gifFigure 41. Output Swing Low vs. Supply Voltage
20204030.gifFigure 43. Output Swing Low vs. Supply Voltage
20204087.gifFigure 2. Input Bias Current vs. VCM
20204086.gifFigure 4. Input Bias Current vs. VCM
20204039.gifFigure 6. Offset Voltage Distribution
20204045.gifFigure 8. TCVOS Distribution
20204021.gifFigure 10. Offset Voltage vs. VCM
20204023.gifFigure 12. Offset Voltage vs. VCM
20204018.gifFigure 14. Offset Voltage vs. Temperature
20204017.gifFigure 16. Open-Loop Frequency Response Gain and Phase
20204015.gifFigure 18. Phase Margin vs. Capacitive Load
20204012.gifFigure 20. CMRR vs. Frequency
20204013.gifFigure 22. Input-Referred Voltage Noise vs. Frequency
20204003.gifFigure 24. Small Signal Step Response
20204006.gifFigure 26. Large Signal Step Response
20204011.gifFigure 28. THD+N vs. Output Voltage
20204008.gifFigure 30. THD+N vs. Frequency
20204037.gifFigure 32. Sourcing Current vs. Supply Voltage
20204034.gifFigure 34. Sourcing Current vs. Output Voltage
20204031.gifFigure 36. Sinking Current vs. Output Voltage
20204025.gifFigure 38. Output Swing High vs. Supply Voltage
20204024.gifFigure 40. Output Swing High vs. Supply Voltage
20204026.gifFigure 42. Output Swing High vs. Supply Voltage