SLVSIP6 June   2026 LMK6L-Q1

ADVMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Environmental Compliance
    4. 6.4 Recommended Operating Conditions
    5. 6.5 Thermal Information
    6. 6.6 Electrical Characteristics
    7. 6.7 Timing Diagrams
    8. 6.8 Typical Characteristics
  8. 7 Parameter Measurement Information
    1. 7.1 Device Output Configurations
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Bulk Acoustic Wave (BAW)
      2. 8.3.2 Device Block-Level Description
      3. 8.3.3 Function Pins
        1. 8.3.3.1 FSEL Implementation
      4. 8.3.4 Output Terminations
        1. 8.3.4.1 Replacing a LVPECL oscillator with the LMK6L-Q1
        2. 8.3.4.2 Replacing a HCSL OSC With the LMK6L-Q1
      5. 8.3.5 Wettable Flanks
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
        1. 9.2.3.1 LVDS Phase Noise Curves
        2. 9.2.3.2 HS-LVDS 1.2Vppd Phase Noise Curves
        3. 9.2.3.3 AC-LVPECL 1.2Vppd Phase Noise Curves
        4. 9.2.3.4 LP-HCSL Phase Noise Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
        1. 9.4.1.1 Providing Thermal Reliability
        2. 9.4.1.2 Recommended Solder Reflow Profile
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Mechanical Data

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8.3.3.1 FSEL Implementation

FSEL automatically disables the /2 or /4 divider if the resulting output frequency violates the minimum output frequency of 50MHz. The output frequency does not change if:

  • FSEL is tied to VDD and FOUT < 100MHz.
  • FSEL is tied to GND and FOUT < 200MHz.
  • FSEL state is changed after power-up (a power cycle is required to change the output frequency).
  • FSEL is controlled by a digital signal. FSEL needs to be tied to GND, VDD, or left open at all times.

Table 8-2 demonstrates FSEL implementation examples. For 312.5MHz and 200MHz, FSEL divides the output frequency, for 156.25MHz and 100MHz, FSEL only divides down when set to VDD, and for 50MHz, FSEL does not change the output frequency.

Table 8-2 FSEL Output Frequency Examples
FOUT FSEL Output Frequency from FSEL (MHz)
312.5 VDD 156.25
Hi-Z or NC 312.5
GND 78.125
156.25 VDD 78.125
Hi-Z or NC 156.25
GND 156.25
100 VDD 50
Hi-Z or NC 100
GND 100
50 VDD 50
Hi-Z or NC 50
GND 50