ZHCSOY4B september   2021  – june 2023 LMK1D2102 , LMK1D2104

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Revision History
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  9. 8 Parameter Measurement Information
  10. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Fail-Safe Inputs
    4. 9.4 Device Functional Modes
      1. 9.4.1 LVDS Output Termination
      2. 9.4.2 Input Termination
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
    3. 10.3 Power Supply Recommendations
    4. 10.4 Layout
      1. 10.4.1 Layout Guidelines
      2. 10.4.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 接收文档更新通知
    3. 11.3 支持资源
    4. 11.4 Trademarks
    5. 11.5 静电放电警告
    6. 11.6 术语表
  13. 12Mechanical, Packaging, and Orderable Information

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10.2.1 Design Requirements

The LMK1D210x shown in Figure 10-2 is configured to fan-out an ADC clock on the first output bank and SYSREF clock on the second output bank for a system utilizing the JESD204B/C ADC. The low output to output skew, very low additive jitter and superior spurious suppression between dual banks makes the LMK1D210x a simple, robust and low-cost solution for distributing various clocks to JESD204B/C AFE systems. The configuration example can drive up to 4 ADC clocks and 4 SYSREF clocks for a JESD204B/C receiver with the following properties:

  • The ADC clock receiver module is typically AC coupled with an LVDS driver such as the LMK1D210x due to differences in common-mode between the driver and receiver. Depending on the receiver, there maybe an option for internal 100-Ω differential termination in which case an external termination would not be required for the LMK1D210x.
  • The SYSREF clock receiver module is typically DC coupled provided the common-mode voltage of the LMK1D210x outputs match with the receiver. An external termination may not be needed in case of an internal termination in the receiver.
  • Unused outputs of the LMK1D device are terminated differentially with a 100-Ω resistor for optimum performance.