SNLS309I April   2010  – December 2014 LMH1983

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configurations and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Frame Timing Outputs Timing Requirements
    7. 7.7 Frame Timing Outputs Switching Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Control of PLL1
      2. 8.3.2  PLL1 Loop Response Design Equations
      3. 8.3.3  Control of PLL2 and PLL3
      4. 8.3.4  Control of PLL4
      5. 8.3.5  Clock Output Jitter
      6. 8.3.6  Lock Determination
      7. 8.3.7  Lock Time Considerations
      8. 8.3.8  LOR Determination
      9. 8.3.9  Output Driver Adjustments
      10. 8.3.10 TOF1 Alignment
      11. 8.3.11 TOF2 and TOF3 Alignment
        1. 8.3.11.1 TOF3 Initialization Set Up
      12. 8.3.12 TOF4 Alignment
    4. 8.4 Device Functional Modes
      1. 8.4.1 Reference Detection
      2. 8.4.2 User Defined Formats
      3. 8.4.3 Auto Format Detection Codes
      4. 8.4.4 Free-Run, Genlock, and Holdover Modes
    5. 8.5 Programming
      1. 8.5.1 I2C Interface Protocol
      2. 8.5.2 Write Sequence
      3. 8.5.3 Read Sequence
    6. 8.6 Register Map
  9. 9 Applications and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Typical Genlock Timing Generation with NTSC 525i/29.97 High Speed Reference
        1. 9.2.1.1 Design Requirements
          1. 9.2.1.1.1 VCXO Selection Criteria
          2. 9.2.1.1.2 Loop Filter Capacitors
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 A/V Clock Generation with Recognized Clock-based Input Reference
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curve
      3. 9.2.3 A/V Clock Generation Using Free-Run Mode
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Detailed Design Procedure
        3. 9.2.3.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Trademarks
    3. 12.3 Electrostatic Discharge Caution
    4. 12.4 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

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4 Revision History

Changes from H Revision (October 2014) to I Revision

  • Updated ESD Ratings tableGo
  • Updated formatting for Typical Characteristics graphs Go

Changes from G Revision (Nov 2012) to H Revision

  • Added Added, updated, or renamed the following sections: Device Information Table, Pin Configuration and Functions, Application and Implementation; Power Supply Recommendations; Layout; Device and Documentation Support; Mechanical, Packaging, and Ordering InformationGo
  • Changed typical value of low output sink current to match simulation value of 1.25 mA. Go
  • Added clarification about PLL4 behavior. Go
  • Added clarification section for LOR Determination Go
  • Changed appearance of Reg 0x11 mode description for clarity.Go
  • Changed register initialization procedure to prevent device from exhibiting poor duty cycle performance on CLKout3 Go
  • Added clarification note about 480i/29.97, 480p/59.94, 576i/25 and 576p/50 resolutions.Go
  • Changed default value for Reg 0x11[3:2] bits. Go
  • Changed Reg 0x11[3:2] description for clarification of TOF1_Sync behavior dependent on LOA windowGo