ZHCSID0D April 2016 – June 2018 LMH1226
PRODUCTION DATA.
Address | Register Name | Bit | Field | Default | Type | Description |
---|---|---|---|---|---|---|
0x00 | Reserved | 7:0 | Reserved | 0x00 | R | Reserved |
0x01 | Reserved | 7:0 | Reserved | 0x40 | R | Reserved |
0x02 | Reserved | 7:0 | Reserved | 0x02 | RW | Reserved |
0x03 | Reserved | 7:0 | Reserved | 0x00 | RW | Reserved |
0x04 | Reserved | 7:0 | Reserved | 0x01 | RW | Reserved |
0x05 | Reserved | 7:0 | Reserved | 0x00 | RW | Reserved |
0x06 | Reserved | 7:0 | Reserved | 0x00 | RW | Reserved |
0x07 | Reserved | 7:0 | Reserved | 0x04 | RW | Reserved |
0x08 | Reserved | 7:0 | Reserved | 0x11 | RW | Reserved |
0x09 | Reserved | 7:0 | Reserved | 0x00 | R | Reserved |
0xE2 | Reset Share/Channel Regs | 7:5 | Reserved | 0x10 | R | Reserved |
4 | reset_done | R | 0 = Internal state machine register initialization not done.
1 = Internal state machine register initialization done. |
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3:1 | Reserved | RW | Reserved | |||
0 | reset_init | RW | 1 = Initialize internal state machine register settings. Refer to the LMH1219 Programming Guide for details. | |||
0xF0 | Device Revision | 7:0 | Version | 0x02 | R | Device Revision |
0xF1 | Device ID | 7:0 | Device_ID | 0x86 | R | For LMH1226, Device ID = 0x86 |
0xFF | Register Communication Control | 7:6 | Reserved | 0x00 | RW | Reserved |
5:4 | los_int_bus_sel | RW | Controls the output on LOCK_N pin
00 = Default behavior (LOCK_N outputs lock status from reclocker) 01 = Reserved 10 = LOS of IN1 11 = Interrupts are output on LOCK_N pin, as determined by CTLE/CDR Page Reg 0x56[6:0] |
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3 | Reserved | RW | Reserved | |||
2 | page_select_enable | RW | 0 = The shared registers are enabled.
1 = Enables communication access to the Register Page specified in Reg 0xFF[1:0]. |
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1:0 | page_select | RW | Enable communication access to a specific Register Page
00 = CTLE/CDR Register Page 01 = Drivers Register Page Other settings are invalid. |