ZHCSHU8F October   2008  – July 2019 LM5575-Q1

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      简化原理图
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Shutdown and Standby
      2. 7.3.2 Current Limit
      3. 7.3.3 Soft Start
      4. 7.3.4 Thermal Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 High-Voltage Start-Up Regulator
      2. 7.4.2 Oscillator and Sync Capability
      3. 7.4.3 Error Amplifier and PWM Comparator
      4. 7.4.4 Ramp Generator
      5. 7.4.5 BOOST Pin
      6. 7.4.6 Maximum Duty Cycle and Input Dropout Voltage
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Bias Power Dissipation Reduction
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Custom Design With WEBENCH® Tools
        2. 8.2.2.2  External Components
        3. 8.2.2.3  R3 (RT)
        4. 8.2.2.4  L1
        5. 8.2.2.5  C3 (CRAMP)
        6. 8.2.2.6  C9, C10
        7. 8.2.2.7  D1
        8. 8.2.2.8  C1, C2
        9. 8.2.2.9  C8
        10. 8.2.2.10 C7
        11. 8.2.2.11 C4
        12. 8.2.2.12 R5, R6
        13. 8.2.2.13 R1, R2, C12
        14. 8.2.2.14 R7, C11
        15. 8.2.2.15 R4, C5, C6
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
    3. 10.3 Thermal Considerations
  11. 11器件和文档支持
    1. 11.1 器件支持
      1. 11.1.1 使用 WEBENCH® 工具创建定制设计
    2. 11.2 接收文档更新通知
    3. 11.3 社区资源
    4. 11.4 商标
    5. 11.5 静电放电警告
    6. 11.6 Glossary
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

8.2.2.15 R4, C5, C6

These components configure the error amplifier gain characteristics to accomplish a stable overall loop gain. One advantage of current mode control is the ability to close the loop with only two feedback components, R4 and C5. The overall loop gain is the product of the modulator gain and the error amplifier gain. The DC modulator gain of the LM5575-Q1 is calculated by Equation 15:

Equation 15. DC Gain(MOD) = Gm(MOD) × RLOAD = 1 × RLOAD

The dominant low frequency pole of the modulator is determined by the load resistance (RLOAD,) and output capacitance (COUT). The corner frequency of this pole is calculated by Equation 16:

Equation 16. fp(MOD) = 1 / (2π RLOAD COUT)

For RLOAD = 5 Ω and COUT = 130 µF then fp(MOD) = 245 Hz

DC Gain(MOD) = 1 × 5 = 14 dB

For the design example of Functional Block Diagram, the measured modulator gain vs. frequency characteristic is shown in Figure 18.

LM5575-Q1 30070815.gif
RLOAD = 5 Ω COUT = 130 µF
Figure 18. Gain and Phase of Modulator

Components R4 and C5 configure the error amplifier as a type II configuration which has a pole at DC and a zero at fZ = 1 / (2πR4C5). The error amplifier zero cancels the modulator pole and leaves a single pole response at the crossover frequency of the loop gain. A single pole response at the crossover frequency yields a very stable loop with 90 degrees of phase margin.

For the design example, a target loop bandwidth (crossover frequency) of 15 kHz was selected. Select the compensation network zero (fZ) at least an order of magnitude less than the target crossover frequency. This constrains the product of R4 and C5 for a desired compensation network zero 1 / (2π R4 C5) to be less than 2 kHz. If the user increases R4 while they proportionally decrease C5, the error amp gain increases. Conversely, if the user decreases R4 while proportionally they increase C5, the error amp gain decreases. For the design example, C5 was selected for 0.01 µF and R4 was selected for 49.9 kΩ. These values configure the compensation network zero at 320 Hz. The error amp gain at frequencies greater than fZ is: R4 / R5, which is approximately 10 (20 dB).

LM5575-Q1 30070816.gifFigure 19. Error Amplifier Gain and Phase

The overall loop can be predicted as the sum (in dB) of the modulator gain and the error amp gain.

LM5575-Q1 30070817.gifFigure 20. Overall Loop Gain and Phase

If a network analyzer is available, the modulator gain can be measured, and the error amplifier gain can be configured for the desired loop transfer function. If a network analyzer is not available, the error amplifier compensation components can be designed with the guidelines given. Step-load transient tests can be performed to verify acceptable performance. The step-load goal is minimum overshoot with a damped response. C6 can be added to the compensation network to decrease noise susceptibility of the error amplifier. The value of C6 must be sufficiently small because the addition of this capacitor adds a pole in the error amplifier transfer function. This pole must be well beyond the loop crossover frequency. A good approximation of the location of the pole added by C6 is: fp2 = fz × C5 / C6.