The input capacitor must be large enough to limit the input voltage ripple to an acceptable level. Equation 18 provides the input capacitance CIN required for a worst-case input ripple of ∆VIN, ripple.
CIN (C1, C10) supplies most of the switch current during the on-time to limit the voltage ripple at the VIN pin. At maximum load current, when the buck switch turns on, the current into the VIN pin quickly increases to the valley current of the inductor ripple and then ramps up to the peak of the inductor ripple during the on-time of the high-side FET. The average current during the on-time is the output load current. For a worst-case calculation, CIN must supply this average load current during the maximum on-time, without letting the voltage at VIN drop more than the desired input ripple. For this design, the input voltage drop is limited to 0.5 V and the value of CIN is calculated using Equation 18.
Based on Equation 18, the value of the input capacitor is determined as approximately 2.5 µF at D = 0.5. Taking into account the decrease in capacitance with applied voltage, two standard value 2.2-µF, 100-V, X7R ceramic capacitors are selected for C1 and C10. The input capacitors must be rated for the maximum input voltage under all operating and transient conditions.
A third input capacitor C2 may be needed in this design as a bypass path for the high-frequency components of input switching current. The value of C2 is 0.47 µF and this bypass capacitor must be placed directly across VIN and PGND (pins 3 and 2) near the IC. The CIN values and location are critical to reducing switching noise and transients.